參數(shù)資料
型號: HYS72D32000GR-8-B
廠商: INFINEON TECHNOLOGIES AG
英文描述: 2.5 V 184-pin Registered DDR-I SDRAM Modules
中文描述: 2.5伏184針注冊的DDR - SDRAM內(nèi)存模塊我
文件頁數(shù): 6/25頁
文件大?。?/td> 315K
代理商: HYS72D32000GR-8-B
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
INFINEON Technologies
6
2002-05-08 (revision 1.0)
Block Diagram: Two Bank 64Mb x 72 DDR-I SDRAM DIMM Modules
HYS 72D64020GR Using x8 Organized SDRAMs on Raw Card Version A
D
Q
4
D
Q
5
D
Q
6
D
Q
7
D
Q
0
D
Q
1
D
Q
2
D
Q
3
DM
D0
DQ
/
D
Q
S
9
DM
D
9
D
Q
12
D
Q
13
D
Q
14
D
Q
15
D
Q
8
D
Q9
D
Q
10
D
Q
11
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D1
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D10
DM1
/
D
Q
S10
D
Q
20
D
Q
21
D
Q
22
D
Q
23
D
Q
16
D
Q
17
D
Q
18
D
Q
1
9
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D2
DM
D11
DM2
/
D
Q
S11
D
Q
28
D
Q
2
9
D
Q
30
D
Q
31
D
Q
24
D
Q
25
D
Q
26
D
Q
27
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D3
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D12
DM3
/
D
Q
S12
D
Q
36
D
Q
37
D
Q
38
D
Q
3
9
D
Q
32
D
Q
33
D
Q
34
D
Q
35
DM
D4
DQ
/
D
Q
S13
DM
D13
D
Q
44
D
Q
45
D
Q
46
D
Q
47
D
Q
40
D
Q
41
D
Q
42
D
Q
43
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D5
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D14
DM5
/
D
Q
S14
D
Q
52
D
Q
53
D
Q
54
D
Q
55
D
Q
48
D
Q
4
9
D
Q
50
D
Q
51
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D6
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D15
D
Q
60
D
Q
61
D
Q
62
D
Q
63
D
Q
56
D
Q
57
D
Q
58
D
Q
5
9
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D7
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D16
DM7
/
D
Q
S16
D
S0
RS0
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
D
Q
S
D
S4
D
Q
S1
D
Q
S5
D
Q
S
D
Q
S
D
Q
S2
D
Q
S
D
Q
S
D
Q
S3
D
Q
S
D
Q
S
DM6
/
D
Q
S15
D
Q
S6
D
Q
S7
CB4
CB5
CB6
CB7
CB0
CB1
CB2
CB3
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D8
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D17
CS
CS
D
Q
S8
DM8
/
D
Q
S17
D
Q
S
D
Q
S
D
Q
S
D
Q
S
D
Q
S
D
Q
S
D
Q
S
D
Q
S
D
Q
S
D
Q
S
D
Q
S
CK0, CK 0 --------- PLL
*
*
Wire per Clock Loading Table
/
Wiring Diagrams
CS1
BA0-BA1
A0-A12
RAS
CAS
CKE0
CKE1
RS1 -
>
CS : SDRAM D
9
-D17
RBA0-RBA1 -
>
BA0-BA1: SDRAMs D0-D17
RA0-RA12 -
>
A0-A12: SDRAMs D0 - D17
RRAS -
>
RAS : SDRAMs D0 - D17
RCAS -
>
CAS : SDRAMs D0 - D17
RCKE0 -
>
CKE: SDRAMs D0 - D8
RCKE1 -
>
CKE: SDRAMs D
9
- D17
CS0
RS0 -
>
CS : SDRAM D0-D8
WE
RWE -
>
WE: SDRAMs D0 - D17
RESET
R
E
G
I
S
T
E
R
PCK
PCK
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
A0
Serial PD
A1
A2
SA0 SA1 SA2
SCL
SDA
Notes:
1. D
Q
-to-I
/
O wiring may be changed within a byte.
2. D
Q/
D
Q
S
/
DM
/
CKE
/
S relationships must be
maintained as shown.
3. D
Q
, D
Q
S, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
STRAP OUT (OPEN): VDD = VDD
Q
5. SDRAM placement alternates between the back
and front of the DIMM.
VDD,
VREF
VSS
VDDID
VDD
Q
Strap: see Note 4
VDDSPD
EEPROM
D0 - D17
D0 - D17
D0 - D17
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