參數(shù)資料
型號: HYS72D16500GR-8-A
廠商: INFINEON TECHNOLOGIES AG
英文描述: Low Profile DDR SDRAM-Modules
中文描述: 超薄DDR內(nèi)存模塊
文件頁數(shù): 21/29頁
文件大?。?/td> 803K
代理商: HYS72D16500GR-8-A
HYS72D[16500/32501]GR-[7/8]-A
Low Profile Registered DDR SDRAM-Modules
SPD Contents
Data Sheet
21
Rev. 1.2, 2004-06
10292003-DNYO-BD9L
4
SPD Contents
Table 12
SPD Codes
Byte#
Description
128MB
x72
1rank
-7
HEX.
80
08
07
0C
0A
01
48
00
04
70
75
128MB
x72
1rank
-8
HEX.
80
08
07
0C
0A
01
48
00
04
80
80
256MB
x72
1rank
-7
HEX.
80
08
07
0C
0B
01
48
00
04
70
75
256MB
x72
1rank
-8
HEX.
80
08
07
0C
0B
01
48
00
04
80
80
0
1
2
3
4
5
6
7
8
9
10
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL = 2.5 7 ns/8 ns
Access Time from Clock at
CL = 2.5
DIMM config
Refresh Rate/Type
SDRAM Width, Primary
Error Checking SDRAM Data
Witdh
Minimum Clock Delay for Back-
to-Back Random Column
Address
Burst Length Supported
Number of SDRAM Ranks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM Module
Attributes
SDRAM Device Attributes:
General
Min. Clock Cycle Time at CAS
Latency = 2
Access Time from Clock for
CL = 2
Minimum Clock Cycle Time for
CL = 1.5
Access Time from Clock at
CL = 1.5
128
256
DDR-SDRAM
12
10/11
1
×
72
0
SSTL_2.5
0.75 ns/0.8 ns
11
12
13
14
ECC
Self-Refresh 15.6 ms
×
8/
×
4
na
02
80
08
08
02
80
08
08
02
80
04
04
02
80
04
04
15
t
CCD
= 1 CLK
01
01
01
01
16
17
18
19
20
21
2, 4 & 8
4
CAS latency = 2 & 2.5
CS latency = 0
Write latency = 1
registered
0E
04
0C
01
02
26
0E
04
0C
01
02
26
0E
04
0C
01
02
26
0E
04
0C
01
02
26
22
Concurrent Auto
Precharge
7.5 ns/10 ns
C0
C0
C0
C0
23
75
A0
75
A0
24
0.75 ns/0.8 ns
75
80
75
80
25
not supported
00
00
00
00
26
not supported
00
00
00
00
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