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參數資料
| 型號： | HYS72D16500GR-8-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Low Profile DDR SDRAM-Modules |
| 中文描述： | 超薄DDR內存模塊 |
| 文件頁數： | 20/29頁 |
| 文件大?。?/td> | 803K |
| 代理商： | HYS72D16500GR-8-A |
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HYS72D[16500/32501]GR-[7/8]-A
Low Profile Registered DDR SDRAM-Modules
Electrical Characteristics
Data Sheet
20
Rev. 1.2, 2004-06
10292003-DNYO-BD9L
Active to Active/Auto-refresh command period
t
RC
Auto-refresh to Active/Auto-refresh command
period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
70
80
—
—
65
75
—
—
ns
ns
2)3)4)5)
t
RFC
2)3)4)5)
t
RCD
t
RP
t
RAP
t
RRD
t
WR
t
DAL
20
20
t
RCD
or
t
RAS
15
15
—
—
20
20
—
—
ns
ns
ns
ns
ns
t
CK
2)3)4)5)
2)3)4)5)
2)3)4)5)
—
—
(
t
wr
/
t
CK
) + (
t
rp
/
t
CK
)
15
15
—
—
2)3)4)5)
2)3)4)5)
2)3)4)5)12)
t
WTR
t
XSNR
t
XSRD
t
REFI
1
80
200
—
—
—
—
15.6
1
75
200
—
—
—
—
15.6
t
CK
ns
t
CK
μ
s
CL > 1.5
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)13)
1) 0
°
C
≤
T
A
≤
70
°
C;
V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V
2) Input slew rate
≥
1 V/ns for DDR266, and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate
≥
1.0 V/ns , slow slew rate
≥
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between
V
OH(ac)
and
V
OL(ac)
.
11)
t
RPRES
is defined for CL = 1.5 operation only
12) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
is equal to the actual system clock
cycle time.
13) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 11
Parameter
AC Timing - Absolute Specifications PC266A and PC2100
Symbol –8
–7
DDR266A
Min.
Unit Note/
Test Condition
1)
DDR200
Min. Max.
Max.
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相關代理商/技術參數 |
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|---|---|
| HYS72D256020GR-7-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?2GB (256Mx72) PC2100 2-bank available 3Q02? |
| HYS72D256020GR-8-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?2GB (256Mx72) PC1600 2-bank available 3Q02? |
| HYS72D256220GBR-5-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184 - Pin Registered Double-Data-Rate SDRAM Module |
| HYS72D256220GBR-6-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184 - Pin Registered Double-Data-Rate SDRAM Module |
| HYS72D256220GBR-7-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184 - Pin Registered Double-Data-Rate SDRAM Module |
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