參數(shù)資料
型號(hào): HYS72D16500GR-7-A
廠商: INFINEON TECHNOLOGIES AG
英文描述: Low Profile DDR SDRAM-Modules
中文描述: 超薄DDR內(nèi)存模塊
文件頁(yè)數(shù): 22/29頁(yè)
文件大?。?/td> 803K
代理商: HYS72D16500GR-7-A
HYS72D[16500/32501]GR-[7/8]-A
Low Profile Registered DDR SDRAM-Modules
SPD Contents
Data Sheet
22
Rev. 1.2, 2004-06
10292003-DNYO-BD9L
27
28
Minimum Row Precharge Time
Minimum Row Act. to Row Act.
Delay
t
RRD
Minimum RAS to CAS Delay
t
RCD
20 ns
Minimum RAS Pulse Width
t
RAS
45 ns/50 ns
Module Rank Density (per Rank) 128 MByte/256 Mbyte
Addr. and Command Setup Time 0.9 ns/1.1 ns
Addr. and Command Hold Time 0.9 ns/1.1 ns
Data Input Setup Time
Data Input Hold Time
Superset Information
Minimum Core Cycle Time
t
RC
Min. Auto Refresh Cmd Cycle
Time
t
FRC
Maximum Clock Cycle Time
t
CK
Max. DQS-DQ Skew tDQSQ
X-Factor tQHS
Superset Information
SPD Revision
Checksum for Bytes 0 - 62
Manufactures JEDEC ID Codes –
Manufactures
Module Assembly Location
Module Part Number
Module Revision Code
Module Manufacturing Date
Module Serial Number
128 to 255 open for Customer use
20 ns
15 ns
50
3C
50
3C
50
3C
50
3C
29
30
31
32
33
34
35
36 to 40
41
42
50
2D
20
90
90
50
50
00
41
4B
50
32
20
B0
B0
60
60
00
46
50
50
2D
40
90
90
50
50
00
41
4B
50
32
40
B0
B0
60
60
00
46
50
0.5 ns/0.6 ns
0.5 ns/0.6 ns
65 ns/70 ns
75 ns/80 ns
43
44
45
46 to 61
62
63
64
65 to 71
72
73 to 90
91 to 92
93 to 94
95 to 98
99 to 127
12 ns
0.5 ns/0.6 ns
0.75 ns/1.0 ns
Revision 0.0
0C
32
75
00
00
A7
C1
Infineon
0C
3C
A0
00
00
9C
C1
Infineon
0C
32
75
00
00
C0
C1
Infineon
0C
3C
A0
00
00
B5
C1
Infineon
Table 12
SPD Codes
(cont’d)
Byte#
Description
128MB
x72
1rank
-7
HEX.
128MB
x72
1rank
-8
HEX.
256MB
x72
1rank
-7
HEX.
256MB
x72
1rank
-8
HEX.
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