- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370806 > HYS72D128020GR-8-A (INFINEON TECHNOLOGIES AG) Cable Termination Tool; For Use With:MediaFlex and Interface Outlets, GigaFlex Modules; Connector Type:Modular RoHS Compliant: NA PDF資料下載
參數(shù)資料
| 型號： | HYS72D128020GR-8-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Cable Termination Tool; For Use With:MediaFlex and Interface Outlets, GigaFlex Modules; Connector Type:Modular RoHS Compliant: NA |
| 中文描述： | 2.5伏184針注冊的DDR - SDRAM內(nèi)存模塊我 |
| 文件頁數(shù)： | 20/25頁 |
| 文件大小： | 315K |
| 代理商： | HYS72D128020GR-8-A |
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
INFINEON Technologies
20
2002-05-08 (revision 1.0)
made High-
Z
, and the differential inputs are powered down — resulting in a total PLL current consumption of less
than 1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is
tied inactive on the DIMM.
This application note describes the required and optional system sequences associated with the DDR Regis-
tered DIMM
'
RESET
'
function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for
a 2-bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely
control CKE to one physical DIMM bank through the use of the RESET pin.
Power-Up Sequence with RESET — Required
1. The system sets RESET at a valid low level.
This is the preferred default state during power-up. This input condition forces all register outputs to a low
state independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable
low-level at the DDR SDRAMs.
2.
The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR
SDRAMs.
3. Stabilization of Clocks to the SDRAM
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches 20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM
PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When
a stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200
μ
sec prior
to SDRAM operation.
4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM con-
nector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these com-
mands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command (with
CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would be a
‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be consistent
with the state of the register outputs.
5. The system switches RESET to a logic
‘
high
’
level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs
must remain stable).
6. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows their clock receivers, data input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDEC-
pproved initialization sequence).
Self Refresh Entry (RESET low, clocks powered off) — Optional
Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down
and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking.
Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption
(RESET low deactivates register CK and CK, data input receivers, and data output drivers).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72D128020GR-8-B | Connector Wall Plate; Color:Almond; Leaded Process Compatible:Yes; No. of Ports:2 RoHS Compliant: Yes |
| HYS72D32000GR-8-A | Connectors, PCB header and jumpers Multipole RoHS Compliant: Yes |
| HYS72D64000GR-8-A | 2.5 V 184-pin Registered DDR-I SDRAM Modules |
| HYS72D64020GR-8-A | 2.5 V 184-pin Registered DDR-I SDRAM Modules |
| HYS72D32000GR-7-B | 2.5 V 184-pin Registered DDR-I SDRAM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72D128020GR-8-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules |
| HYS72D128020GU-7-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Unbuffered DDR-I SDRAM Modules |
| HYS72D128020GU-8-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Unbuffered DDR-I SDRAM Modules |
| HYS72D128021GR-7-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules |
| HYS72D128021GR-8-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules |
發(fā)布緊急采購，3分鐘左右您將得到回復。