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參數(shù)資料
| 型號： | HYS72D128020GR-8-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Cable Termination Tool; For Use With:MediaFlex and Interface Outlets, GigaFlex Modules; Connector Type:Modular RoHS Compliant: NA |
| 中文描述： | 2.5伏184針注冊的DDR - SDRAM內(nèi)存模塊我 |
| 文件頁數(shù)： | 12/25頁 |
| 文件大?。?/td> | 315K |
| 代理商： | HYS72D128020GR-8-A |
HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
INFINEON Technologies
12
2002-05-08 (revision 1.0)
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0
°
C
≤
T
A
≤
70
°
C
;
V
DD
Q
= 2.5V
±
0.2V
;
V
DD
= 2.5V
±
0.2V)
Symbol
Parameter
DDR266A
-7
DDR200
-8
Unit
Notes
Min
Max
Min
Max
t
AC
D
Q
output access time from CK
/
CK
0.75
+
0.75
0.8
+
0.8
ns
1-4
t
D
Q
SCK
D
Q
S output access time from CK
/
CK
0.75
+
0.75
0.8
+
0.8
ns
1-4
t
CH
CK high-level width
0.45
0.55
0.45
0.55
t
CK
1-4
t
CL
CK low-level width
0.45
0.55
0.45
0.55
t
CK
1-4
t
HP
Clock Half Period
min (t
CL,
t
CH)
min (t
CL,
t
CH)
ns
1-4
t
CK
Clock cycle time
CL = 2.5
7
12
8
12
ns
1-4
t
CK
CL = 2.0
7.5
12
10
12
ns
1-4
t
DH
D
Q
and DM input hold time
0.5
0.6
ns
1-4
t
DS
D
Q
and DM input setup time
0.5
0.6
ns
1-4
t
IPW
Control and Addr. input pulse width (each
input)
2.2
2.5
ns
1, 10
t
DIPW
D
Q
and DM input pulse width (each input)
1.75
2
ns
1-4,
11
t
H
Z
Data-out high-impedence time from CK
/
CK
0.75
+
0.75
0.8
+
0.8
ns
1-4, 5
t
L
Z
Data-out low-impedence time from CK
/
CK
0.75
+
0.75
0.8
+
0.8
ns
1-4, 5
t
D
Q
SS
Write command to 1st D
Q
S latching transition
0.75
1.25
0.75
1.25
t
CK
1-4
t
D
Q
S
Q
D
Q
S-D
Q
skew
(for D
Q
S & associated D
Q
signals)
+
0.5
+
0.6
ns
1-4
t
Q
HS
Data hold skew factor
+ 0.75
+ 1.0
ns
1-4
t
Q
H
Data Output hold time from D
Q
S
t
HP
-t
Q
HS
t
HP
-t
Q
HS
ns
1-4
t
D
Q
SL,H
D
Q
S input low (high) pulse width (write cycle)
0.35
0.35
t
CK
1-4
t
DSS
D
Q
S falling edge to CK setup time (write
cycle)
0.2
0.2
t
CK
1-4
t
DSH
D
Q
S falling edge hold time from CK (write
cycle)
0.2
0.2
t
CK
1-4
t
MRD
Mode register set command cycle time
14
16
ns
1-4
t
WPRES
Write preamble setup time
0
0
ns
1-4, 7
t
WPST
Write postamble
0.40
0.60
0.40
0.60
t
CK
1-4, 6
t
WPRE
Write preamble
0.25
0.25
t
CK
1-4
t
IS
Address and control
input setup time
fast slew rate
0.
9
1.1
ns
2-4,
10,11
slow slew rate
1.0
1.1
ns
t
IH
Address and control
input hold time
fast slew rate
0.
9
1.1
ns
slow slew rate
1.0
1.1
ns
t
RPRE
Read preamble
0.
9
1.1
0.
9
1.1
t
CK
1-4
t
RPST
Read postamble
0.40
0.60
0.40
0.60
t
CK
1-4
t
RAS
Active to Precharge command
45
120,000
50
120,000
ns
1-4
t
RC
Active to Active
/
Auto-refresh command period
65
70
ns
1-4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72D128020GR-8-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules |
| HYS72D128020GU-7-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Unbuffered DDR-I SDRAM Modules |
| HYS72D128020GU-8-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Unbuffered DDR-I SDRAM Modules |
| HYS72D128021GR-7-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules |
| HYS72D128021GR-8-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules |
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