參數(shù)資料
型號(hào)： HYS64D128320GU-5-B
廠商： INFINEON TECHNOLOGIES AG
英文描述： 184-Pin Unbuffered Dual-In-Line Memory Modules
中文描述： 184引腳緩沖雙列內(nèi)存模組
文件頁(yè)數(shù)： 21/40頁(yè)
文件大小： 1374K
代理商： HYS64D128320GU-5-B
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Data Sheet
21
Rev. 1.0, 2004-05
10042003-RYU3-RQON
3.2
Current Conditions and Specification
I
DD
Conditions
Parameter
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE
≤
V
IL,MAX
Precharge Floating Standby Current
CS
≥
V
IH,,MIN
, all banks idle; CKE
≥
V
IH,MIN
;
address and other control inputs changing once per clock cycle;
V
IN
=
V
REF
for DQ, DQS and DM.
Precharge Quiet Standby Current
CS
≥
V
IHMIN
, all banks idle; CKE
≥
V
IH,MIN
;
V
IN
=
V
REF
for DQ, DQS and DM;
address and other control inputs stable at
≥
V
IH,MIN
or
≤
V
IL,MAX
.
Active Power-Down Standby Current
one bank active; power-down mode; CKE
≤
V
ILMAX
;
V
IN
=
V
REF
for DQ, DQS and DM.
Active Standby Current
one bank active; CS
≥
V
IH,MIN
; CKE
≥
V
IH,MIN
;
t
RC
=
t
RAS,MAX
;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B;
I
OUT
= 0 mA
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
t
RC
=
t
RFCMIN
, burst refresh
Self-Refresh Current
CKE
≤
0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
Symbol
I
DD0
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P
I
DD3N
I
DD4R
I
DD4W
I
DD5
I
DD6
I
DD7
相關(guān)PDF資料
PDF描述
HYS72D128320GU-5-B Category 6 Termination Kit; For Use With:GigaBIX? Cross-Connect or Interconnect Systems; Leaded Process Compatible:Yes RoHS Compliant: Yes
HYS72D128320HU-6-B Connector Wall Plate; Color:Almond; Leaded Process Compatible:Yes; Series:PS6+; No. of Ports:2 RoHS Compliant: Yes
HYS64D64300GU 184-Pin Unbuffered Dual-In-Line Memory Modules
HYS64D64300HU-5-B 184-Pin Unbuffered Dual-In-Line Memory Modules
HYS64D128320HU-5-B 184-Pin Unbuffered Dual-In-Line Memory Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS64D128320GU-6-A 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Unbuffered DDR-I SDRAM Modules
HYS64D128320GU-6-B 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules
HYS64D128320HU-5-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:42184-Pin Unbuffered Double-Data-Rate Memory Modules
HYS64D128320HU-5-C 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Unbuffered Double Data Rate SDRAM
HYS64D128320HU-6-B 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules
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