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| 型號： | HYS64D128320GU-5-B |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 184-Pin Unbuffered Dual-In-Line Memory Modules |
| 中文描述： | 184引腳緩沖雙列內存模組 |
| 文件頁數(shù)： | 18/40頁 |
| 文件大?。?/td> | 1374K |
| 代理商： | HYS64D128320GU-5-B |
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HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Data Sheet
18
Rev. 1.0, 2004-05
10042003-RYU3-RQON
Input Leakage Current
I
I
–2
2
μ
A
Any input 0 V
≤
V
IN
≤
V
DD
;
All other pins not under test
= 0 V
8)9)
DQs are disabled;
0 V
≤
V
OUT
≤
V
DDQ
8)
V
OUT
= 1.95 V
8)
Output Leakage Current
I
OZ
–5
5
μ
A
Output High Current,
Normal Strength Driver
Output Low
Current, Normal Strength
Driver
I
OH
—
–16.2
mA
I
OL
16.2
—
mA
V
OUT
= 0.35 V
8)
1) 0
°
C
≤
T
A
≤
70
°
C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions,
V
DDQ
must be less than or equal to
V
DD
.
4) Peak to peak AC noise on
V
REF
may not exceed ± 2%
V
REF (DC)
.
V
REF
is also expected to track noise variations in
V
DDQ
.
5)
V
TT
is not applied directly to the device.
V
TT
is a system supply for signal termination resistors, is expected to be set equal
to
V
REF
, and must track variations in the DC level of
V
REF
.
6)
V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until
V
REF
stabilizes.
9) Values are shown per DDR SDRAM component
Table 13
Parameter
AC Timing - Absolute Specifications for PC3200 and PC2700
Symbol
–5
DDR400B
Min.
–0.5
–0.6
0.45
0.45
min. (
t
CL
,
t
CH
)
5
–6
DDR333
Min.
–0.7
–0.6
0.45
0.45
min. (
t
,
t
CH
)
—
Unit
Note/ Test
Condition
1)
Max.
+0.5
+0.6
0.55
0.55
Max.
+0.7
+0.6
0.55
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
t
AC
t
DQSCK
t
CH
t
CL
t
HP
t
CK
ns
ns
t
CK
t
CK
ns
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
8
—
CL = 3.0
2)3)4)5)
6
12
7.5
12
ns
CL = 2.5
2)3)4)5)
7.5
12
7.5
12
ns
CL = 2.0
2)3)4)5)
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width
(each input)
t
DH
t
DS
t
IPW
0.4
0.4
2.2
—
—
—
0.45
0.45
2.2
—
—
—
ns
ns
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)6)
Table 12
Parameter
Electrical Characteristics and DC Operating Conditions
(cont’d)
Symbol
Min.
Values
Typ.
Unit Note/Test Condition
1)
Max.
相關PDF資料 |
PDF描述 |
|---|---|
| HYS72D128320GU-5-B | Category 6 Termination Kit; For Use With:GigaBIX? Cross-Connect or Interconnect Systems; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| HYS72D128320HU-6-B | Connector Wall Plate; Color:Almond; Leaded Process Compatible:Yes; Series:PS6+; No. of Ports:2 RoHS Compliant: Yes |
| HYS64D64300GU | 184-Pin Unbuffered Dual-In-Line Memory Modules |
| HYS64D64300HU-5-B | 184-Pin Unbuffered Dual-In-Line Memory Modules |
| HYS64D128320HU-5-B | 184-Pin Unbuffered Dual-In-Line Memory Modules |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYS64D128320GU-6-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Unbuffered DDR-I SDRAM Modules |
| HYS64D128320GU-6-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules |
| HYS64D128320HU-5-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:42184-Pin Unbuffered Double-Data-Rate Memory Modules |
| HYS64D128320HU-5-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Unbuffered Double Data Rate SDRAM |
| HYS64D128320HU-6-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules |
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