參數(shù)資料
型號(hào): HYS 64V64220GU
廠商: SIEMENS AG
英文描述: 3.3 V 64M 64-Bit SDRAM Modules(3.3 V 64M 64/72-Bit 2 個(gè)存儲(chǔ)體的 SDRAM 模塊)
中文描述: 3.3伏6400 64位SDRAM模塊(3.3伏6400 64/72-Bit 2個(gè)存儲(chǔ)體的內(nèi)存模塊)
文件頁數(shù): 12/17頁
文件大?。?/td> 131K
代理商: HYS 64V64220GU
HYS 64/72V64220GU
SDRAM-Modules
Data Book
12
3.00
7. If
t
T
is longer than 1 ns, a time (
t
T
– 1) ns has to be added to this parameter.
8. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR)
commands must be given to “wake-up” the device.
9. Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
10.Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self-Refresh Exit is not complete until a time period equal to
t
RC
is satisfied
after the Self Refresh Exit command is registered.
11.This is referenced to the time at which the output achieves the open circuit condition, not to
output voltage levels.
Note: *)
256MByte PC133 modules with place code “-C” indicating Rev. C dies are used as memory
components are fully PC100 2-2-2 backwards compatible, where PC133 modules with place code
“-A” operates as PC100 3-2-2 on a 100 Mhz memory bus.
A serial presence detect storage device - E
2
PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E
2
PROM device during module
production using a serial presence detect protocol (I
2
C synchronous 2-wire bus).
50 pF
I/O
Measurement conditions for
t
AC
and
t
OH
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
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