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參數(shù)資料
| 型號： | HYM7V63801BTFG-75 |
| 英文描述： | x64 SDRAM Module |
| 中文描述： | X64的內(nèi)存模塊 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 172K |
| 代理商： | HYM7V63801BTFG-75 |
PC133 SDRAM Unbuffered DIMM
HYM7V73A801B F-Series
Rev. 1.1/Apr.01
5
SERIAL PRESENCE DETECT
BYTE
NUMBER
FUNCTION
DESCRIBED
FUNCTION
-75
VALUE
-75
NOTE
BYTE0
# of Bytes Written into Serial Memory
at Module Manufacturer
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
Data Width of This Assembly (Continued)
Voltage Interface Standard of This Assembly
SDRAM Cycle Time @ /CAS Latency=3
Access Time from Clock @ /CAS Latency=3
DIMM Configuration Type
128 Bytes
80h
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
BYTE10
BYTE11
256 Bytes
SDRAM
12
9
1 Bank
72 Bits
-
LVTTL
7.5ns
5.4ns
ECC
15.625
μ
s
/ Self Refresh Supported
x8
x8
08h
04h
0Ch
09h
01h
48h
00h
01h
75h
54h
02h
1
BYTE12
Refresh Rate/Type
80h
BYTE13
BYTE14
Primary SDRAM Width
Error Checking SDRAM Width
Minimum Clock Delay Back to Back Random
Column Address
Burst Lengths Supported
# of Banks on Each SDRAM Device
SDRAM Device Attributes, CAS # Latency
SDRAM Device Attributes, CS # Latency
SDRAM Device Attributes, Write Latency
SDRAM Module Attributes
08h
08h
BYTE15
tCCD = 1 CLK
01h
BYTE16
BYTE17
BYTE18
BYTE19
BYTE20
BYTE21
1,2,4,8,Full Page
4 Banks
/CAS Latency=2,3
/CS Latency=0
/WE Latency=0
Neither Buffered nor Registered
+/-10% voltage tolerance, Burst
Read Single bit Write, Precharge
All, Auto Precharge, Early RAS
Precharge
10ns
6ns
-
-
20ns
15ns
20ns
45ns
64MB
1.5ns
0.8ns
1.5ns
0.8ns
8Fh
04h
06h
01h
01h
00h
2
BYTE22
SDRAM Device Attributes, General
0Eh
BYTE23
BYTE24
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
BYTE31
BYTE32
BYTE33
BYTE34
BYTE35
BYTE36
–61
BYTE62
BYTE63
BYTE64
BYTE65
~71
SDRAM Cycle Time @ /CAS Latency=2
Access Time from Clock @ /CAS Latency=2
SDRAM Cycle Time @ /CAS Latency=1
Access Time from Clock @ /CAS Latency=1
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active Delay (tRRD)
Minimum /RAS to /CAS Delay (tRCD)
Minimum /RAS Pulse width (tRAS)
Module Bank Density
Command and Address Signal Input Setup Time
Command and Address Signal Input Hold Time
Data Signal Input Setup Time
Data Signal Input Hold Time
A0h
60h
00h
00h
14h
0Fh
14h
2Dh
10h
15h
08h
15h
08h
Superset Information (may be used in future)
-
00h
SPD Revision
Checksum for Bytes 0~62
Manufacturer JEDEC ID Code
Intel SPD 1.2
-
Hynix JEDEC ID
12h
B0h
ADh
3, 4
....Manufacturer JEDEC ID Code
Unused
FFh
BYTE72
Manufacturing Location
Hynix (Korea Area)
HSA (United States Area)
HSU (Europe Area)
HSJ (Japan Area)
Asia Area
0*h
1*h
2*h
3*h
4*h
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYM7V651601BTFG | 16Mx64|3.3V|P/S|x16|SDR SDRAM - Unbuffered DIMM 128MB |
| HYM7V651601BTFG-10P | x64 SDRAM Module |
| HYM7V651601BTFG-10S | x64 SDRAM Module |
| HYM7V651601BTFG-8 | x64 SDRAM Module |
| HYM7V65401BLTQG | 8Mx64|3.3V|P/S|x8|SDR SDRAM - SO DIMM 64MB |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYM7V651601BTFG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16Mx64|3.3V|P/S|x16|SDR SDRAM - Unbuffered DIMM 128MB |
| HYM7V651601BTFG-10P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
| HYM7V651601BTFG-10S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
| HYM7V651601BTFG-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
| HYM7V65401BLTQG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx64|3.3V|P/S|x8|SDR SDRAM - SO DIMM 64MB |
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