參數(shù)資料
型號: HYM7V63801BTFG-75
英文描述: x64 SDRAM Module
中文描述: X64的內(nèi)存模塊
文件頁數(shù): 2/13頁
文件大?。?/td> 172K
代理商: HYM7V63801BTFG-75
PC133 SDRAM Unbuffered DIMM
HYM7V73A801B F-Series
Rev. 1.1/Apr.01
2
PIN DESCRIPTION
PIN NAME
DESCRIPTION
CK0~CK3
Clock Inputs
The System Clock Input. All other inputs are registered to the
SDRAM on the rising edge of CLK.
CKE0
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
/S0, /S2
Chip Select
Enables or disables all inputs except CK, CKE and DQM.
BA0, BA1
SDRAM Bank Address
Select bank to be activated during /RAS activity.
Select bank to be read/written during /CAS activity
A0~A11
Address Inputs
Row address : RA0~RA11, Column address : CA0~CA8
Auto-precharge flag : A10
/RAS
Row Address Strobe
/RAS define the operation.
Refer to the function truth table for details.
/CAS
Column Address Strobe
/CAS define the operation.
Refer to the function truth table for details.
/WE
Write Enable
/WE define the operation.
Refer to the function truth table for details.
DQM0~DQM7
Data Input/Output Mask
Controls output buffers in read mode and masks input data in
write mode.
DQ0~DQ63
Data Input/Output
Multiplexed data input/output pins
CB0~CB7
ECC Data Input/Output
Error Checking and Correction Bits
VCC
Power Supply (3.3V)
Power supply for internal circuits and input/output buffers
VSS
Ground
Ground
SCL
SPD Clock Input
Serial Presence Detect Clock Input
SDA
SPD Data Input/Output
Serial Presence Detect Data input/output
SA0~SA2
SPD Address Input
Serial Presence Detect Address input
WP
Write Protect for SPD
Write Protect for Serial Presence Detect on DIMM
NC
No Connect
No Connect or Don’t Use
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