參數(shù)資料
型號: HYM72V8005GU-50
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 3.3V 8M x 64-Bit EDO-DRAM Module 3.3V 8M x 72-Bit EDO-DRAM Module
中文描述: 8M X 72 EDO DRAM MODULE, 50 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 13/17頁
文件大?。?/td> 90K
代理商: HYM72V8005GU-50
HYM 64(72)V8005/45GU-50/-60
8M x 64/72 DRAM Module
Semiconductor Group
13
Capacitance
T
A
= 0 to 70 °C;
V
CC
= 3.3 V
±
0.3 V;
f
= 1 MHz
Hyper Page Mode (EDO) Read-modify-Write Cycle
Hyper page mode (EDO) read-write
cycle time
t
PRWC
58
68
ns
CAS precharge to WE
t
CPWD
41
49
ns
CAS-before-RAS Refresh Cycle
CAS setup time
t
CSR
t
CHR
t
RPC
t
WRP
t
WRH
10
10
ns
CAS hold time
10
10
ns
RAS to CAS precharge time
5
5
ns
Write to RAS precharge time
10
10
ns
Write hold time referenced to RAS
10
10
ns
Parameter
Symbol
Limit Values
Unit
min.
max.
Input Capacitance (A0 to A11,(A12))
C
I1
C
I2
C
I3
C
I4
C
IO1
C
s
Cs
55
pF
Input Capacitance (RAS0, RAS2)
50
pF
Input Capacitance (CAS0-CAS7)
10
pF
Input Capacitance (WE0,WE2,OE0,OE2)
50
pF
I/O Capacitance (DQ0-DQ63,CB0-CB8)
11
pF
Input Capacitance (SCL, SA0-2)
8
pF
Input/Output Capacitance (SDA)
10
pF
AC Characteristics
(cont’d)
5)6)
T
A
= 0 to 70 °C,
V
CC
= 3.3 V
±
0.3 V,
t
T
= 2 ns
16E
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
min.
max.
min.
max.
相關(guān)PDF資料
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HYM64V8005GU-50 3.3V 8M x 64-Bit EDO-DRAM Module 3.3V 8M x 72-Bit EDO-DRAM Module
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參數(shù)描述
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