參數(shù)資料
型號: HYM72V4005GU-60
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 3.3V 4M x 64-Bit EDO-DRAM Module 3.3V 4M x 72-Bit EDO-DRAM Module
中文描述: 4M X 72 EDO DRAM MODULE, 60 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 8/11頁
文件大小: 70K
代理商: HYM72V4005GU-60
Semiconductor Group
8
HYM72V4005/15GS-50/-60
4M x 72-ECC EDO-Module
Output buffer turn-off delay from OE
t
OEZ
t
DZC
t
DZO
t
CDD
t
ODD
18
20
ns
9,17
CAS delay time from Din
0
0
ns
18
Data to OE low delay
0
0
ns
18
CAS high to data delay
15
18
ns
9,19
OE high to data delay
15
18
ns
9,19
Write Cycle
Write command hold time
t
WCH
t
WP
t
WCS
t
RWL
t
CWL
t
DS
t
DH
13
15
ns
9
Write command pulse width
8
10
ns
Write command setup time
2
2
ns
11,20
Write command to RAS lead time
18
20
ns
9
Write command to CAS lead time
13
15
ns
Data setup time
-2
-2
ns
10,21
Data hold time
13
15
ns
9,21
Read-Modify-Write Cycle
Read-write cycle time
RAS to WE delay time
t
RWC
t
RWD
t
CWD
t
AWD
t
OEH
118
66
143
77
ns
ns
9
11,21
CAS to WE delay time
29
34
ns
11,21
Column address to WE delay time
41
49
ns
11,21
OE command hold time
8
11
ns
10
Hyper Page Mode (EDO) Cycle
Hyper page mode cycle time
t
PC
t
CP
t
CPA
t
COH
t
RAS
t
RHCP
t
OES
20
25
ns
CAS precharge time
8
10
ns
Access time from CAS precharge
32
37
ns
9,13
Output data hold time
3
3
ns
10
RAS pulse width
50
200k
60
200k
ns
CAS precharge to RAS Delay
32
37
ns
9
OE setup time prior to CAS
5
5
ns
AC Characteristics
(cont’d) (note: 5,6,7,8)
T
A
= 0 to 70 °C,
V
CC
= 3.3
±
0.3 V
Parameter
Symbol
-50
-60
Unit
Note
min.
max.
min.
max.
相關(guān)PDF資料
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HYM72V4005GS-50 4M x 72-Bit EDO-DRAM Module
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HYM72V4045GU-50 3.3V 4M x 64-Bit EDO-DRAM Module 3.3V 4M x 72-Bit EDO-DRAM Module
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