參數(shù)資料
型號(hào): HYM72V4005GU-60
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 3.3V 4M x 64-Bit EDO-DRAM Module 3.3V 4M x 72-Bit EDO-DRAM Module
中文描述: 4M X 72 EDO DRAM MODULE, 60 ns, DMA168
封裝: DIMM-168
文件頁(yè)數(shù): 6/11頁(yè)
文件大?。?/td> 70K
代理商: HYM72V4005GU-60
Semiconductor Group
6
HYM72V4005/15GS-50/-60
4M x 72-ECC EDO-Module
Capacitance
T
A
= 0 to 70 °C;
V
CC
= 3.3 V
±
0.3V;
f
= 1 MHz
Average
V
CC
supply current during RAS
only refresh cycles:
-50 version
-60 version
(RAS cycling, CAS =
V
IH
, t
RC
=
t
RC
min.)
Average
V
CC
supply current during hyper
page mode (EDO):
I
CC3
1800
1620
mA
mA
2)4)
-50 version
-60 version
(RAS =
V
IL,
CAS, address cycling
t
PC
=
t
PC
min.)
Standby
V
CC
supply current
(RAS = CAS =
V
CC
– 0.2 V,
one address change within 15,6
μ
s trc)
Average
V
CC
supply current during
CAS-before-RAS refresh mode:
I
CC4
1260
990
mA
mA
2)3)4)
I
CC5
30
mA
-50 version
-60 version
(RAS, CAS cycling
, t
RC
=
t
RC
min.)
I
CC6
1800
1620
mA
mA
2)4)
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A11,B0)
C
I1
C
I2
C
I3
C
I4
C
IO1
10
pF
Input capacitance (RAS0, RAS2)
50
pF
Input capacitance (CAS0, CAS4)
15
pF
Input capacitance (WE0,WE2,OE0,OE2)
15
pF
I/O capacitance (DQ0-DQ71)
15
pF
Parameter
Symbol
Limit Values
Unit
Test
Condition
min.
max.
相關(guān)PDF資料
PDF描述
HYM72V4005GS-50 4M x 72-Bit EDO-DRAM Module
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HYM72V4045GU-50 3.3V 4M x 64-Bit EDO-DRAM Module 3.3V 4M x 72-Bit EDO-DRAM Module
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