參數(shù)資料
型號(hào): HYM321000S-50
廠商: SIEMENS A G
元件分類(lèi): DRAM
英文描述: 1M x 32-Bit Dynamic RAM Module 2M x 16-Bit Dynamic RAM Module
中文描述: 1M X 32 FAST PAGE DRAM MODULE, 50 ns, SMA72
封裝: SIMM-72
文件頁(yè)數(shù): 7/10頁(yè)
文件大?。?/td> 80K
代理商: HYM321000S-50
Semiconductor Group
7
HYM 321000S/GS-50/-60
1M
×
32-Bit
AC Characteristics
5)6)
M16F
T
A
= 0 to 70 °C,
V
CC
= 5 V
±
10 %,
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
min.
max.
min.
max.
common parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
T
t
REF
90
110
ns
RAS precharge time
30
40
ns
RAS pulse width
50
10k
60
10k
ns
CAS pulse width
13
10k
15
10k
ns
Row address setup time
0
0
ns
Row address hold time
8
10
ns
Column address setup time
0
0
ns
Column address hold time
10
15
ns
RAS to CAS delay time
18
37
20
45
RAS to column address delay time
13
25
15
30
ns
RAS hold time
13
15
ns
CAS hold time
50
60
ns
CAS to RAS precharge time
5
5
ns
Transition time (rise and fall)
3
50
3
50
ns
7
Refresh period
16
16
ms
Read Cycle
Access time from RAS
t
RAC
t
CAC
t
AA
t
RAL
t
RCS
t
RCH
t
RRH
50
60
ns
8, 9
Access time from CAS
13
15
ns
8, 9
Access time from column address
25
30
ns
8,10
Column address to RAS lead time
25
30
ns
Read command setup time
0
0
ns
Read command hold time
0
0
ns
11
Read command hold time referenced to
RAS
0
0
ns
11
CAS to output in low-Z
t
CLZ
t
OFF
0
0
ns
8
Output buffer turn-off delay
0
13
0
15
ns
12
相關(guān)PDF資料
PDF描述
HYM321000GS-50 1M x 32-Bit Dynamic RAM Module 2M x 16-Bit Dynamic RAM Module
HYM321160GS-60 1M x 32-Bit Dynamic RAM Module
HYM321160S-60 1M x 32-Bit Dynamic RAM Module
HYM321160GS-70 1M x 32-Bit Dynamic RAM Module
HYM321160S 1M x 32-Bit Dynamic RAM Module
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