參數資料
型號: HYB3166165AT-50
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 4M x 16-Bit Dynamic RAM
中文描述: 4M X 16 EDO DRAM, 50 ns, PDSO50
文件頁數: 4/29頁
文件大?。?/td> 284K
代理商: HYB3166165AT-50
Semiconductor Group
4
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
TRUTH TABLE
FUNCTION
RAS LCAS UCAS
WE
OE
ROW
ADD
COL
ADD
I/O1-
I/O16
Standby
H
H - X
H - X
X
X
X
X
High Impedance
Read:Word
L
L
H
H
L
ROW
COL
Data Out
Read:Lower Byte
L
L
H
H
L
ROW
COL
Lower Byte:Data Out
Upper-Byte:High-Z
Read:Upper Byte
L
H
L
H
L
ROW
COL
Lower Byte:High-Z
Upper Byte:Data Out
Write:Word
(Early-Write)
L
L
L
L
X
ROW
COL
Data In
Write:Lower Byte
(Early-Write)
L
L
H
L
X
ROW
COL
Lower Byte:Data Out
Upper-Byte:High-Z
Write:Upper Byte
(Early Write)
L
H
L
L
X
ROW
COL
Lower Byte:High-Z
Upper Byte:Data Out
Read-Modify-
Write
L
L
L
H - L
L - H ROW
COL
Data Out, Data In
Hyper Page Mode
Read (Word)
1st
Cycle
L
H - L
H - L
H
L
ROW
COL
Data Out
Hyper Page Mode
Read (Word)
2nd
Cycle
L
H - L
H - L
H
L
n/a
COL
Data Out
Hyper Page Mode
Early Write(Word)
1st
Cycle
L
H - L
H - L
L
X
ROW
COL
Data In
Hyper Page Mode
Early Write(Word)
2nd
Cycle
L
H - L
H - L
L
X
n/a
COL
Data In
Hyper Page Mode
RMW
1st
Cycle
L
H - L
H - L
H - L
L - H ROW
COL
Data Out, Data In
Hyper Page Mode
RMW
2st
Cycle
L
H - L
H - L
H - L
L - H n/a
COL
Data Out, Data In
RAS only refresh
L
H
H
X
X
ROW
n/a
High Impedance
CAS-before-RAS
refresh
H - L L
L
H
X
X
n/a
High Impedance
Test Mode Entry
H - L L
L
L
X
X
n/a
High Impedance
Hidden Refresh
(Read)
L-H-
L
L
L
H
L
ROW
COL
Data Out
Hidden Refresh
(Write)
L-H-
L
L
L
L
X
ROW
COL
Data In
Self Refresh
(L-version only)
H-L
L
H
X
X
X
X
High Impedance
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HYB3164165BT-50 4M x 16-Bit Dynamic RAM
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