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參數(shù)資料
| 型號： | HYB3117805BSJ-50- |
| 廠商： | SIEMENS AG |
| 英文描述： | 2M x 8 - Bit Dynamic RAM 2k Refresh |
| 中文描述： | 200萬× 8 -位動態(tài)隨機存儲器2k刷新 |
| 文件頁數(shù)： | 10/25頁 |
| 文件大小： | 258K |
| 代理商： | HYB3117805BSJ-50- |
Semiconductor Group
10
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Notes:
1) All voltages are referenced to
V
SS
.
2)
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3)
I
CC1
and
I
CC4
depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during
a hyper page mode (EDO) cycle
5) An initial pause of 200
μ
s is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume
t
T
= 2 ns.
7)
V
I
H
(min.)
and
V
I
L (max.)
are reference levels for measuring timing of input signals. Transition times are also
measured between
V
I
H
and
V
I
L
.
8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined
by the latter of tRAC, tCAC, tAA,tCPA, tOEA . tCAC is measured from tristate.
9) Operation within the
t
RCD (max.)
limit ensures that
t
RAC (max.)
can be met.
t
RCD (max.)
is specified as a reference point
only. If
t
RCD
is greater than the specified
t
RCD (max.)
limit, then access time is controlled by
t
CAC
.
10) Operation within the
t
)
limit ensures that
t
RAC (max.)
can be met.
t
RAD (max.)
is specified as a reference point
only. If
t
RAD
is greater than the specified
t
RAD (max.)
t
AA
.
11) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
12)
t
OFF (max.)
,
t
OEZ (max.)
define the time at which the output achieves the open-circuit conditions and are not
referenced to output voltage levels.
t
OFF
is referenced from the rising edge of RAS or CAS, whichever occurs
last.
13) Either
t
DZC
or
t
DZO
must be satisfied.
14) Either
t
CDD
or
t
ODD
must be satisfied.
15)
t
,
t
,
t
and
t
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If
t
>
t
, the cycle is an early write cycle and data out pin will remain
open-circuit (high impedance) through the entire cycle; if
t
>
t
,
t
>
t
and
t
>
t
,
the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above
sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR
refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the
refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately
after exit from Self Refresh
相關PDF資料 |
PDF描述 |
|---|---|
| HYB3117805BSJ-50 | 2M x 8-Bit Dynamic RAM 2k Refresh |
| HYB 3117805BSJ-50 | 2M*8 Bit Dynamic RAM 2k Refresh（Hyper Page Mode EDO） |
| HYB 3117805BSJ-60 | 2M×8 - Bit Dynamic RAM 2k Refresh（Hyper Page Mode EDO） |
| HYB 5117805BSJ-50 | 2M×8 - Bit Dynamic RAM 2k Refresh（Hyper Page Mode EDO） |
| HYB 5117805BSJ-60 | 2M×8 - Bit Dynamic RAM 2k Refresh（Hyper Page Mode EDO） |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3117805BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2M x 8-Bit Dynamic RAM 2k Refresh |
| HYB3117805BSJ-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EDO Page Mode DRAM |
| HYB3118160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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