參數(shù)資料
型號: HYB3116405BJ-70
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 3.3V 4M x 4-Bit EDO-Dynamic RAM
中文描述: 4M X 4 EDO DRAM, 70 ns, PDSO24
文件頁數(shù): 7/26頁
文件大?。?/td> 285K
代理商: HYB3116405BJ-70
Semiconductor Group
7
HYB 3116(7)405BJ/BT(L) -50/-60/-70
3.3V 4Mx4-DRAM
Average
V
CC
supply current, during RAS-only
refresh cycles:
-50 ns version
-60 ns version
-70 ns version
(RAS cycling: CAS =
V
IH
,
t
RC
=
t
RC
min.)
Average
V
CC
supply current, during hyper page
mode EDO): -50 ns version
I
CC3
100(120)
90 (110)
80 (100)
mA
mA
mA
2) 4)
2) 4)
2) 4)
-60 ns version
-70 ns version
(RAS =
V
IL
, CAS, address cycling,
t
PC
=
t
PC
min.
)
Standby
V
CC
supply current
(RAS = CAS =
V
CC
– 0.2 V)
I
CC4
70 (70)
55 (55)
45 (45)
mA
mA
mA
2) 3) 4)
2) 3) 4)
2) 3) 4)
I
CC5
1
200
mA
μ
A
1)
L-version
Average
V
CC
supply current, during CAS-
before-RAS refresh mode: -50 ns version
-60 ns version
-70 ns version
(RAS, CAS cycling,
t
RC
=
t
RC
min.)
Average Self Refresh Current
I
CC6
100(120)
90 (110)
80 (100)
mA
mA
mA
2) 4)
2) 4)
2) 4)
(CBR cylce with tRAS>TRASSmin., CAS held low,
WE=Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
I
CC7
_
1
250
mA
μ
A
L-version
Capacitance
T
A
= 0 to 70 °C,
V
CC
= 3.3 V
±
0.3V,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A10, A11)
C
I1
C
I2
C
IO
5
pF
Input capacitance (RAS, CAS, WE, OE)
7
pF
I/O capacitance (I/O1 - I/O4)
7
pF
DC Characteristics
(values in brackets for HYB3117405)
T
A
= 0 to 70 °C,
V
SS
= 0 V,
V
CC
= 3.3 V
±
0.3 V,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
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參數(shù)描述
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