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參數(shù)資料
| 型號(hào)： | HYB25D256160CE-6 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256 Mbit Double Data Rate SDRAM |
| 中文描述： | 256兆雙倍數(shù)據(jù)速率SDRAM |
| 文件頁(yè)數(shù)： | 44/94頁(yè) |
| 文件大?。?/td> | 3326K |
| 代理商： | HYB25D256160CE-6 |
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Data Sheet
49
Rev. 1.6, 2004-12
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Functional Description
Figure 24
Write to Read: Min. DQSS, Odd Number of Data (3-bit Write), Interrupting (CL2; BL8)
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 3 data elements are written.
2 subsequent elements of data in are applied in the programmed order following DI a-b.
tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
Don’t Care
T1
T2
T3
T4
T5
T6
NOP
Read
Write
NOP
CK
Command
Address
BAa, COL b
BAa, COL n
tWTR
DI a-b
DQS
DQ
CL = 2
tDQSS (min)
DM
12
2
1 = This bit is correctly written into the memory array if DM is low.
2 = These bits are incorrectly written into the memory array if DM is low.
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PDF描述 |
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| HYB25D256160BC-6 | Tools, Crimp; For Use With:Crimp terminal 12-60 AWG; Crimp Tool:Hand Crimp Tool |
| HYB39S256800DC-6 | 256 MBit Synchronous DRAM |
| HYB39S256160DC-6 | 256 MBit Synchronous DRAM |
| HYB39S256800DC-7 | 256 MBit Synchronous DRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| HYB25D256160CEL-6 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Double-Data-Rate SDRAM |
| HYB25D256160CF-5 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Double-Data-Rate SDRAM |
| HYB25D256160CF-6 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Double-Data-Rate SDRAM |
| HYB25D256160CT-5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
| HYB25D256160CT-6 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Double-Data-Rate SDRAM |
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