參數(shù)資料
型號(hào)： HYB25D256160BT-7F
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256 Mbit Double Data Rate SDRAM
中文描述： 256兆雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù)： 90/94頁
文件大?。?/td> 3326K
代理商： HYB25D256160BT-7F
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
System Characteristics for DDR SDRAMs
Data Sheet
90
Rev. 1.6, 2004-12
08012003-8754-PAQX
6
System Characteristics for DDR SDRAMs
The following specification parameters are required in systems using DDR400, DDR333 & DDR266 devices to
ensure proper system performance. These characteristics are for system simulation purposes and are not subject
to production test - verified by design/characterization.
Table 25
Input Slew Rate for DQ, DQS, and DM
AC Characteristics
Symbol
DDR400
DDR333
DDR266
Units Notes
Parameter
Min. Max. Min. Max. Min. Max.
DM/DQS inout slew rate measured berween
V
IH(DC), VIL (DC), and VIL(DC), VIH (DC)
DCSLEW 0.5
4.0
0.5
4.0
0.5
4.0
V/ns
1)2)
1)
Pullup slew rate is characterized under the test conditions as shown in Figure 52.
2) DQS, DM, amd DQ input slew rate is specified to prevent doble clocking of data and preserve setup and hold times. Signal
transitions through the DC region must be monotonic.
Table 26
Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate
tIS
t
IH
Units
Notes
0.5 V/ns
0
ps
1)
1) A derating factor will be used to increase
t
IS and tIH in the case where the input slew rate is below 0.5 V/ns as shown in
Table 26. The input slew rate is based on the lesser of the slew rates determined by either
V
IH (AC) to VIL (AC) or VIH (DC)
to
V
IL (DC), similarly for rising transitions. Aderating factor applies to speed bins DDR200, DDR266, and DDR333.
0.4 V/ns
+50
0
ps
0.3 V/ns
+100
0
ps
Table 27
Input/Output Setup and Hold TIme Derating for Slew Rate
I/O Input Slew Rate
tDS
t
DH
Units
Notes
0.5 ns/V
0
ps
1)
1) Table 27 is used to increase
t
DS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based
on the lesser of the AV – AC slew rate and the DC – DC slew rate. The input slew rate is based on the lesser of the slew
rates determined by either
V
IH (AC) to VIL (AC) or VIH (DC) to VIL (DC), and similarly for rising transitions. A derating factor
applies to speed bins DDR200, DDR266 and DDR333.
0.4 ns/V
+75
ps
0.3 ns/V
+100
ps
Table 28
Input/Output Setup and Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate
tDS
t
DH
Units
Notes
±0.0 ns/V
0
ps
1)
1) A derating factor will be used to increase
t
DS and tDH in the case where DQ, DM and DQS slew rates differ, as shown in
Figure 27 & Figure 28. Input slew rate is based on the larger of AC – AC delta rise, fall rate and DC – DC delta rise, fall
rate. Input slew rate is based on the lesser of the slew rates determined by either
V
IH (AC) to VIL (AC) or VIH (DC) to VIL
(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as:{1/(Slew Rate1)} – {1/(Slew Rate2)}
For example: If Slew Rate 1 is 0.5 V/ns and Slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is –0.5 ns/V. Using the
table given, this would result in the need for an increase in
t
DS and tDH of 100 ps. A derating factor applies to speed bins
DDR200, DDR266, and DDR333.
±0.25 ns/V
+50
ps
±0.5 ns/V
+100
ps
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