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| 型號： | HYB25D256160BCL-7F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256 Mbit Double Data Rate SDRAM |
| 中文描述： | 256兆雙倍數(shù)據(jù)速率SDRAM |
| 文件頁數(shù)： | 22/94頁 |
| 文件大?。?/td> | 3326K |
| 代理商： | HYB25D256160BCL-7F |
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Data Sheet
29
Rev. 1.6, 2004-12
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Functional Description
Table 8
Truth Table 1a: Commands
Name (Function)
CS
RAS CAS WE Address
MNE
Notes
Deselect (NOP)
H
X
NOP
1)2)
No Operation (NOP)
L
H
X
NOP
Active (Select Bank And Activate Row)
L
H
Bank/Row ACT
Read (Select Bank And Column, And Start Read Burst)
L
H
L
H
Bank/Col
Read
Write (Select Bank And Column, And Start Write Burst)
L
H
L
Bank/Col
Write
Burst Terminate
L
H
L
X
BST
Precharge (Deactivate Row In Bank Or Banks)
L
H
L
Code
PRE
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
L
H
X
AR/SR 1)7)8)
Mode Register Set
L
Op-Code
MRS
1) CKE is HIGH for all commands shown except Self Refresh.
V
REF must be maintained during Self Refresh operation
2) Deselect and NOP are functionally interchangeable.
3) BA0-BA1 provide bank address and A0-A12 provide row address.
4) BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16, i = 9 for x8 and 9, 11 for x4);
A10 HIGH enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature.
5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read
bursts with Auto Precharge enabled or for write bursts.
6) A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
7) This command is Auto Refresh if CKE is HIGH; Self Refresh if CKE is LOW.
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1,
BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to
be written to the selected Mode Register).
Table 9
Truth Table 1b: DM Operation
Name (Function)
DM
DQs
Notes
Write Enable
L
Valid
1)
1) Used to mask write data; provided coincident with the corresponding data.
Write Inhibit
HX
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| HYB25D256160BCL-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
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| HYB25D256160BT-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B |
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