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參數(shù)資料
| 型號： | HYB25D128400CT-7 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit Double Data Rate SDRAM |
| 中文描述： | 128兆雙倍數(shù)據(jù)速率SDRAM |
| 文件頁數(shù)： | 71/85頁 |
| 文件大?。?/td> | 2653K |
| 代理商： | HYB25D128400CT-7 |
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Data Sheet
71
Rev. 1.0, 2004-04
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Electrical Characteristics
4.3.1
Legend: A = Activate, R = Read, RA = Read with Autoprecharge, P = Precharge, N = NOP or DESELECT
I
DD
Current Measurement Conditions
I
DD1
: Operating Current: One Bank Operation
1. General test condition
a) Only one bank is accessed with
t
RC,MIN
.
b) Burst Mode, Address and Control inputs are changing once per NOP and DESELECT cycle.
c) 50% of data changing at every transfer
d)
I
OUT
= 0 mA.
2. Timing patterns
a)
DDR266A
(133 MHz, CL = 2):
t
CK
= 7.5 ns, BL = 4,
t
RCD
= 3
×
t
CK
,
t
RC
= 9
×
t
CK
,
t
RAS
= 5
×
t
CK
Setup: A0 N N R0 N P0 N N N
Read: A0 N N R0 N P0 N NN - repeat the same timing with random address changing
b)
DDR333B
(166 MHz, CL = 2.5):
t
CK
= 6 ns, BL = 4,
t
RCD
= 3
×
t
CK
,
t
RC
= 9
×
t
CK
,
t
RAS
= 5
×
t
CK
Setup: A0 N N R0 N P0 N N N
Read: A0 N N R0 N P0 N N N - repeat the same timing with random address changing
c)
DDR400B
(200 MHz, CL = 3):
t
CK
= 5 ns, BL = 4,
t
RCD
= 3
×
t
CK
,
t
RC
= 11
×
t
CK
,
t
RAS
= 8
×
t
CK
Setup:A0 N N R0 N N N N P0 N N
Read: A0 N N R0 N N N N P0 N N -repeat the same timing with random address changing
I
DD7
: Operating Current: Four Bank Operation
1. General test condition
a) Four banks are being interleaved with
t
RCMIN
.
b) Burst Mode, Address and Control inputs on NOP edge are not changing.
c) 50% of data changing at every transfer
d)
I
OUT
= 0 mA.
2. Timing patterns
a)
DDR266A
(133 MHz, CL = 2):
t
CK
= 7.5 ns, BL = 4,
t
RRD
= 2
×
t
CK
,
t
RCD
= 3
×
t
CK
,
t
RAS
= 5
×
t
CK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3
Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing
b)
DDR333B
(166 MHz, CL = 2.5):
t
CK
= 6 ns, BL = 4,
t
RRD
= 2
×
t
CK
,
t
RCD
= 3
×
t
CK
,
t
RAS
= 5
×
t
CK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3
Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing
c)
DDR400B
(200 MHz, CL = 3):
t
CK
= 5 ns, BL = 4,
t
RRD
= 2
×
t
CK
,
t
RCD
= 3 *
×
t
CK
,
t
RAS
= 8
×
t
CK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N
Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N - repeat the same timing with random address
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| HYB25D128800AT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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| HYB25D128800AT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?128Mb (16Mx8) DDR200 (2-2-2)? |
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