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參數(shù)資料
| 型號： | HYB25D128400ATL-6 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit Double Data Rate SDRAM |
| 中文描述： | 128兆雙倍數(shù)據(jù)速率SDRAM |
| 文件頁數(shù)： | 53/85頁 |
| 文件大小： | 3085K |
| 代理商： | HYB25D128400ATL-6 |
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Data Sheet
53
Rev. 1.0, 2004-04
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
3.5.5
Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs
when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input
and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down mode, so for maximum
power savings, the user has the option of disabling the DLL prior to entering Power-down. In that case, the DLL
must be enabled after exiting power-down, and 200 clock cycles must occur before a Read command can be
issued. In power-down mode, CKE Low and a stable clock signal must be maintained at the inputs of the
DDR SDRAM, and all other input signals are “Don’t Care”. However, power-down duration is limited by the refresh
requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled
power-down mode.
The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or Deselect
command). A valid, executable command may be applied one clock cycle later.
Power-Down
Figure 31
Power Down
t
IS
t
IS
CK
CK
CKE
Command
No column
access in
progress
VALID
NOP
VALID
Don’t Care
Exit
power down
mode
Enter Power Down mode
(Burst Read or Write operation
must not be in progress)
NOP
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| HYB25D128400ATL-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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| HYB25D128400CE-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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