參數(shù)資料
型號(hào)： HYB25D128323CL-3.6
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128 Mbit DDR SGRAM
中文描述： 128兆的DDR SGRAM
文件頁(yè)數(shù)： 17/53頁(yè)
文件大小： 1166K
代理商： HYB25D128323CL-3.6
Data Sheet
17
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
read bursts, the data valid window coincides with the high or low level of the DQSx signals. During write bursts,
the DQSx signal marks the center of the valid data window. Data is available at every rising and falling edge of
DQSx, therefore the data transfer rate is doubled.
For Read accesses, the DQSx signals are aligned to the clock signal CLK.
3.4
Special Signal Description
3.4.1
The DDR SGRAM operates with a differential clock (CLK and CLK#) input. CLK is used to latch the address and
command signals. Data input and DMx signals are latched with DQSx. The DDR SGRAM implements a Delay
Locked Loop circuit (DLL) which tracks both edges of the CLK input signal and aligns the DQS output edges with
the CLK input edges.
The minimum and maximum clock cycle time is defined by
t
CK
. The maximum value for
t
CK
is defined to provide a
lower bound for the operation frequency of the internal DLL circuit. The minimum and maximum clock duty cycle
are specified using the minimum clock high time
t
CH
and the minimum clock low time
t
CL
respectively.
The internal DLL circuit requires additional 200 clock cycles after DLL reset for internal clock stabilization.
Clock Signal
3.4.2
Like single data rate SGRAMs, each combination of RAS#, CAS# and WE# input in conjunction with CS# input at
a rising edge of the clock determines a DDR SGRAM command.
Command Inputs and Addresses
Figure 5
Command and Address Signal Timing
3.4.3
Data Strobe and Data Mask
3.4.3.1
The Data Strobes provide a 3-state output signal to the receiver circuits of the controller during a read burst. The
data strobe signal goes
t
RPRE
clock cycle low before data is driven by the DDR SGRAM and then toggles low to
high and high to low till the end of the burst. The CAS latency is specified to the first low to high transition. The
edges of the Output Data signals and the edges of the data strobe signals during a read are nominally coincident
with edges of the input clock. The tolerance of these edges is specified by the parameters
t
AC
and
t
DQSCK
and is
referenced to the crossing point of the CLK and CLK# signal. The
t
DQSQ
timing parameter describes the skew
between the data strobe edge and the output data edge.
The following table summarizes the mapping of DQSx and DMx signals to the data bus.
Operation at Burst Reads
Valid
Valid
CLK, CLK#
Address,
CS#, RAS#,
CAS#, WE#,
CKE
VIH
VTT
VIL
VIH
VIL
t
IS
t
IH
相關(guān)PDF資料
PDF描述
HYB25D128323CL-4.5 128 Mbit DDR SGRAM
HYB25D128323CL3.6 128 Mbit DDR SGRAM
HYB25D128323C-3.3 128 Mbit DDR SGRAM
HYB25D128323C-3.6 128 Mbit DDR SGRAM
HYB25D128323C-4.5 128 Mbit DDR SGRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB25D128323CL4.5 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323C-L4.5 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323CL-4.5 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128400AT 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
HYB25D128400AT-6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
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