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參數資料
| 型號： | HYB25D128323CL-3.6 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit DDR SGRAM |
| 中文描述： | 128兆的DDR SGRAM |
| 文件頁數： | 15/53頁 |
| 文件大小： | 1166K |
| 代理商： | HYB25D128323CL-3.6 |
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A7
mode
Data Sheet
15
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
3
Register Set
3.1
Mode Register
The mode register stores the data for controlling the various operating modes of the DDR SGRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL ON and various vendor specific options. The default
value of the mode register is not defined. Therefore the mode register must be written after power up to operate
the DDR SGRAM. The DDR SGRAM should be activated with CKE already high prior to writing into the Mode
Register. The Mode Register is written by using the MRS command. The state of the address signals registered
in the same cycle as MRS command is written in the mode register. The value can be changed as long as all banks
are in the idle state.
The mode register is divided into various fields depending on functionality. The burst length uses A2.. A0, CAS
latency (read latency from column address) uses A6.. A4. A7 is used for test mode, A8 is used for DLL Reset. A7,
A8 and BA1 must be set to low for normal DDR SGRAM operation. A9.. A11 is reserved for future use. BA0 selects
Extended Mode Register Setup operation when set to 1. Refer to the table for specific codes for various burst
length, addressing modes and CAS latencies.
Figure 3
Mode Register Bitmap
BA1
BA0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DLL
RFU
TM
CAS Latency
BT
Burst Length
0
1
Normal
Testmode
Testmode
A8
0
1
DLL Reset
Yes
DLL Reset
No
A3
0
1
Type
Sequential
Reserved
Burst Type
Address Bus
Mode Register
Latency
2
A6
A5
A4
All other Reserved
3
0
0
0
1
1
CAS Latency
Length
2
A2
A1
A0
4
8
0
0
0
0
1
1
1
1
Sequential
Interleave
0
8
4
2
Burst Length
All other Reserved
BA0
0
1
Accessed Register
Extend. Mode Reg.
Extended Mode
Register Access
Mode Register
0
0
A11
A10
RFU
RFU
1
4
1
0
0
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PDF描述 |
|---|---|
| HYB25D128323CL-4.5 | 128 Mbit DDR SGRAM |
| HYB25D128323CL3.6 | 128 Mbit DDR SGRAM |
| HYB25D128323C-3.3 | 128 Mbit DDR SGRAM |
| HYB25D128323C-3.6 | 128 Mbit DDR SGRAM |
| HYB25D128323C-4.5 | 128 Mbit DDR SGRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HYB25D128323CL4.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323C-L4.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323CL-4.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128400AT | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128400AT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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