參數(shù)資料
型號(hào): HYB25D128323C-L4.5
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128 Mbit DDR SGRAM
中文描述: 128兆的DDR SGRAM
文件頁(yè)數(shù): 28/53頁(yè)
文件大?。?/td> 1166K
代理商: HYB25D128323C-L4.5
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Data Sheet
28
V1.7, 2003-07
Figure 20
Data Mask Timing
3.5.14
The Autoprecharge command is issued by setting column address A8 high when a Read or a Write command is
asserted to the DDR SGRAM. If A8 is low when Read or Write command is issued, a normal Read or Write burst
operation is executed and the bank remains active at the end of the burst sequence. When the Auto Precharge
command is activated, the active bank automatically begins to precharge at the earliest possible moment during
the Read or Write cycle after
t
RAS(min.)
is satisfied.
Autoprecharge Operation
3.5.15
If a Read with Auto-precharge command is initiated, the DDR SGRAM automatically enters the precharge
operation BL/2 clock cycles after the READA command and
t
RAS(min.)
is satisfied. If
t
RAS(min.)
has not been satisfied
yet, an internal interlock will delay the precharge operation until it is satisfied. Once the precharge operation has
started, the bank cannot be reactivated and the new command can not be asserted until the Precharge time (
t
RP
)
has been satisfied.
Read with Autoprecharge (READA)
D-in
2
CLK
WRITE
DQSx
DQx
D-in
0
Command
DMx
NOP
NOP
NOP
NOP
NOP
NOP
D-in
1
D-in
3
NOP
Burst length = 8
D-in
6
D-in
4
D-in
5
D-in
7
Data is masked out
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