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參數(shù)資料
| 型號： | HYB25D128323C-L3.6 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit DDR SGRAM |
| 中文描述： | 128兆的DDR SGRAM |
| 文件頁數(shù)： | 24/53頁 |
| 文件大?。?/td> | 1166K |
| 代理商： | HYB25D128323C-L3.6 |
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HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Data Sheet
24
V1.7, 2003-07
Figure 16
Power Down Mode timing
3.5.9
Burst mode operation is used to provide a constant flow of data to the memory (write cycle) or from the memory
(read cycle). The burst length is programmable and set by address bits A0 - A3 during the Mode Register Setup
command. The burst length controls the number of words that will be output after a read command or the number
of words to be input after a write command. One word is 32 bits wide. The sequential burst length can be set to 2,
4 or 8 data words.
Burst Mode Operation
3.5.10
The Burst Read operation is initiated by issuing a READ command at the rising edge of the clock after
t
RCD
from
the bank activation. The address inputs (A7.. A0) determine the starting address for the burst. The burst length (2,
4 or 8) must be defined in the Mode Register. The first data after the READ command is available depending on
the CAS latency. The subsequent data is clocked out on the rising and falling edge of DQSx until the burst is
completed. The DQSx signal is generated by the DDR SGRAM during Burst Read Operations.
Burst Read Operation: (READ)
Table 6
Burst Length
Burst Mode and Sequence
Starting Column Address
A2
Order of Access within a Burst
Type = Sequential
0 - 1
1 - 0
0 - 1 - 2 - 3
1 - 2 - 3 - 0
2 - 3 - 0 - 1
3 - 0 - 1 - 2
0 - 1 - 2 - 3 - 4 - 5 - 6 - 7
1 - 2 - 3 - 4 - 5 - 6 - 7 - 0
2 - 3 - 4 - 5 - 6 - 7 - 0 - 1
3 - 4 - 5 - 6 - 7 - 0 - 1 - 2
4 - 5 - 6 - 7 - 0 - 1 - 2 - 3
5 - 6 - 7 - 0 - 1 - 2 - 3 - 4
6 - 7 - 0 - 1 - 2 - 3 - 4 - 5
7 - 0 - 1 - 2 - 3 - 4 - 5 - 6
A1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
4
0
0
1
1
0
0
1
1
0
0
1
1
8
0
0
0
0
1
1
1
1
Clk
Command
PRE
t
PDEX
CKE
NOP
Any
Command
Power Down
Mode entry
NOP
NOP
DESEL
Power Down
Mode exit
NOP
DESEL
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| HYB25D128323C | 128 Mbit DDR SGRAM |
| HYB25D128323C-3 | 128 Mbit DDR SGRAM |
| HYB25D128400AT | 128 Mbit Double Data Rate SDRAM |
| HYB25D128400AT-6 | 128 Mbit Double Data Rate SDRAM |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D128323CL4.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323C-L4.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323CL-4.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128400AT | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128400AT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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