參數(shù)資料
型號(hào)： HYB25D128323C-L3.6
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128 Mbit DDR SGRAM
中文描述： 128兆的DDR SGRAM
文件頁(yè)數(shù)： 22/53頁(yè)
文件大?。?/td> 1166K
代理商： HYB25D128323C-L3.6
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Data Sheet
22
V1.7, 2003-07
Figure 13
Precharge Command Timing
3.5.6
The self refresh mode can be used to retain the data in the DDR SGRAM if the chip is powered down. To set the
DDR SGRAM into a self refreshing mode, a Self Refresh command must be issued and CKE held low at the rising
edge of the clock. Once the self Refresh command is initiated, CKE must stay low to keep the device in Self
Refresh mode. During the Self refresh mode, all of the external control signals are disabled except CKE. The clock
is internally disabled during Self Refresh operation to reduce power. An internal timing generator guarantees the
self refreshing of the memory content. To exit the Self Refresh mode, a stable external clock is needed for the DLL
before returning CKE high. After the Power Down Exit time(
t
PDEX
), a Deselect or NOP command is issued and CKE
is held high for longer than
t
SREX
in order to lock the DLL.
Self Refresh
Table 5
A8/AP
Precharge Control
BA1
BA0
Precharged
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Bank A Only
Bank B Only
Bank C Only
Bank D Only
All Banks
Clk
Command
ACT
t
RC
Addresses
Bank A
PRE
NOP
ACT
Bank A
t
RAS
t
RP
NOP
Bank A
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB25D128323CL4.5 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323C-L4.5 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323CL-4.5 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128400AT 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
HYB25D128400AT-6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
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