參數(shù)資料
型號(hào): HYB25D128160TC-5
廠商: INFINEON TECHNOLOGIES AG
英文描述: MEMORY SPECTRUM
中文描述: 記憶譜
文件頁數(shù): 9/85頁
文件大?。?/td> 3085K
代理商: HYB25D128160TC-5
Data Sheet
9
Rev. 1.0, 2004-04
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Overview
The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto
Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent
operation, thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
Note:The functionality described and the timing specifications included in this data sheet are for the DLL Enabled
mode of operation.
Table 1
Part Number
1)
Ordering Information
1) HYB: designator for memory components
25D: DDR SDRAMs at
V
DDQ
= 2.5 V
128: 128-Mbit density
400/800/160: Product variations x4, x8 and x16
C: Die revision C
T/E/C: Package type TSOP and FBGA
L: Low power version (optional) - these components are specifically selected for low
I
DD6
Self Refresh currents
-5/6/7/7F/8: speed grade - see
Table 1
Org.
CAS-RCD-
RP
Latencies
Clock
(MHz)
CAS-RCD-
RP
Latencies
Clock
(MHz)
Speed
Package
HYB25D128160CT-5
HYB25D128160CT-6
HYB25D128800CT-6
HYB25D128800CTL-6
HYB25D128400CT-7
HYB25D128400CC-6
×
16
×
16
×
8
×
8
×
4
×
4
3-3-3
2.5-3-3
200
166
2.5-3-3
2-3-3
166
133
DDR400B
DDR333
P-TSOPII-66-1
DDR266A
DDR333
P-FBGA-60-2
HYB25D128160CE–5
HYB25D128400CE–6
HYB25D128800CE–6
HYB25D128800CEL–6
HYB25D128160CE–6
×
16
×
4
×
8
×
8
×
16
3-3-3
2.5-3-3
200
166
2.5-3-3
2-3-3
166
133
DDR400B
DDR333
P-TSOPII-66-1
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