參數(shù)資料
型號(hào): HYB25D128160CT-5
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128 Mbit Double Data Rate SDRAM
中文描述: 128兆雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù): 23/85頁
文件大小: 3085K
代理商: HYB25D128160CT-5
Data Sheet
23
Rev. 1.0, 2004-04
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
3.2.4
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A11 set to zero,
and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with
bits A7 and A9-A11 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register
Set command issued to reset the DLL should always be followed by a Mode Register Set command to select
normal operating mode.
All other combinations of values for A7-A11 are reserved for future use and/or test modes. Test modes and
reserved states should not be used as unknown operation or incompatibility with future versions may result.
Operating Mode
Figure 6
Required CAS Latencies
NOP
NOP
NOP
NOP
NOP
Read
CAS Latency = 2, BL = 4
Shown with nominal t
AC
, t
DQSCK
, and t
DQSQ
.
CK
CK
Command
DQS
DQ
Don’t Care
CL=2
NOP
NOP
NOP
NOP
NOP
Read
CAS Latency = 2.5, BL = 4
CK
CK
Command
DQS
DQ
CL=2.5
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