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參數(shù)資料
| 型號(hào)： | HY5DU281622ET-36 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 128M(8Mx16) GDDR SDRAM |
| 中文描述： | 8M X 16 DDR DRAM, 0.6 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁(yè)數(shù)： | 13/34頁(yè) |
| 文件大?。?/td> | 379K |
| 代理商： | HY5DU281622ET-36 |
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Rev. 0.5 / Jan. 2005
13
HY5DU281622ET
CKE FUNCTION TRUTH TABLE
Note :
When CKE=L, all DQ and UDQS/LDQS should be in Hi-Z state.
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.
2. All commands can be stored after 2 clocks from low to high transition of CKE.
3. Illegal, if CK is suspended or stopped during the power down mode.
4. Self refresh can be asserted only from the all banks idle state.
5. Disabling CK may cause malfunction of any banks which are in active state.
Current
State
CKEn-
1
CKEn
/CS
/RAS
/CAS
/WE
/ADD
Action
SELF
REFRESH
1
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit self refresh, enter idle after tSREX
L
H
L
H
H
H
X
Exit self refresh, enter idle after tSREX
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP, continue self refresh
POWER
DOWN
2
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit power down, enter idle
L
H
L
H
H
H
X
Exit power down, enter idle
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP, continue power down mode
ALL BANKS
IDLE
4
H
H
X
X
X
X
X
See operation command truth table
H
L
L
L
L
H
X
Enter self refresh
H
L
H
X
X
X
X
Exit power down
H
L
L
H
H
H
X
Exit power down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
H
X
X
ILLEGAL
H
L
L
L
L
L
X
ILLEGAL
L
L
X
X
X
X
X
NOP
ANY STATE
OTHER
THAN
ABOVE
H
H
X
X
X
X
X
See operation command truth table
H
L
X
X
X
X
X
ILLEGAL
5
L
H
X
X
X
X
X
INVALID
L
L
X
X
X
X
X
INVALID
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