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參數(shù)資料
| 型號： | HY5DU281622ET-30 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 128M(8Mx16) GDDR SDRAM |
| 中文描述： | 8M X 16 DDR DRAM, 0.6 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數(shù)： | 3/34頁 |
| 文件大?。?/td> | 379K |
| 代理商： | HY5DU281622ET-30 |
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Rev. 0.5 / Jan. 2005
3
HY5DU281622ET
DESCRIPTION
The Hynix HY5DU281622ET is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for
the point-to-point applications which require high densities and high bandwidth.
The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
2.8V +/- 0.1V V
DD
and V
DDQ
power supply
supports 400/375/350/333/300MHz
2.5V +/- 5% V
DD
and V
DDQ
power supply
supports 275/250/200/166MHz
All inputs and outputs are compatible with SSTL_2
interface
JEDEC Standard 400 mil x 875 mil 66 Pin TSOP II,
with 0.65mm pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (UDQS,LDQS)
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Write mask byte controls by DM (UDM,LDM)
Programmable /CAS Latency 5, 4 and 3 are sup-
ported
Programmable Burst Length 2, 4 and 8 with both
sequential and interleave mode
Internal 4 bank operation with single pulsed /RAS
tRAS Lock-Out function are supported
Auto refresh and self refresh are supported
4096 refresh cycles / 32ms
Full strength, Half strength and Weak Impedance
driver options controlled by EMRS
ORDERING INFORMATION
Part No.
Power
Supply
Clock
Frequency
Max Data Rate
interface
Package
HY5DU281622ET-25
VDD/VDDQ=2.8V
400MHz
800Mbps/pin
SSTL_2
400 x 875mil
2
66 Pin TSOP II
HY5DU281622ET-26
375MHz
750Mbps/pin
HY5DU281622ET-28
350MHz
700Mbps/pin
HY5DU281622ET-30
333MHz
666Mbps/pin
HY5DU281622ET-33
300MHz
600Mbps/pin
HY5DU281622ET-36
VDD/VDDQ=2.5V
275MHz
550Mbps/pin
HY5DU281622ET-4
250MHz
500Mbps/pin
HY5DU281622ET-5
200MHz
400Mbps/pin
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5DU281622ET-33 | 128M(8Mx16) GDDR SDRAM |
| HY5DU281622ET-36 | 128M(8Mx16) GDDR SDRAM |
| HY5DU281622ET-4 | 128M(8Mx16) GDDR SDRAM |
| HY5DU281622ET-5 | 128M(8Mx16) GDDR SDRAM |
| HY5DU283222AF | 128M(4Mx32) GDDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU281622ET-33 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DU281622ET-36 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DU281622ET-4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DU281622ET-5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DU281622ETP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb DDR SDRAM |
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