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參數(shù)資料
| 型號： | HY51V65163HGJ-6 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 4M x 16Bit EDO DRAM |
| 中文描述： | 4M X 16 EDO DRAM, 60 ns, PDSO50 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-50 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 96K |
| 代理商： | HY51V65163HGJ-6 |
HY51V(S)65163HG/HGL
Rev.0.1/Apr.01
7
Write Cycles
Read-Modify-Write Cycles
Refresh cycles
Parameter
Symbol
-45
-50
-60
Unit
Note
Min
Max
Min
Max
Min
Max
Write command set-up time
tWCS
0
-
0
-
0
-
ns
14,21
Write command hold time
t
WCH
7
-
8
-
10
-
ns
21
Write command pulse width
tWP
7
-
8
-
10
-
ns
Write command to /RAS lead time
t
RWL
12
-
13
-
15
-
ns
Write command to /CAS lead time
t
CWL
7
-
8
-
10
-
ns
23
Data-in set-up time
tDS
0
-
0
-
0
-
ns
15, 23
Data-in hold time
tDH
7
-
8
-
10
-
ns
15, 23
Parameter
Symbol
-45
-50
-60
Unit
Note
Min
Max
Min
Max
Min
Max
Read-modify-write cycle time
tRWC
101
-
116
-
140
-
ns
/RAS to /WE delay time
t
RWD
63
-
67
-
79
-
ns
14
/CAS to /WE delay time
tCWD
30
-
30
-
34
-
ns
14
Column address to /WE delay time
t
AWD
40
-
42
-
49
-
ns
14
/OE hold time from /WE
t
OEH
12
-
13
-
15
-
ns
Parameter
Symbol
-45
-50
-60
Unit
Note
Min
Max
Min
Max
Min
Max
/CAS set-up time
( /CAS-before-/RAS Refresh Cycle)
tCSR
5
-
5
-
5
-
ns
21
/CAS hold time
( /CAS-before-/RAS Refresh Cycle)
t
CHR
7
-
8
-
10
-
ns
22
/WE set-up time
( /CAS-before-/RAS Refresh Cycle)
tWRP
0
-
0
-
0
-
ns
/WE hold time
( /CAS-before-/RAS Refresh Cycle)
t
WRH
7
-
8
-
10
-
ns
/RAS precharge to /CAS hold time
( /CAS-before-/RAS Refresh Cycle)
t
RPC
5
-
5
-
5
-
ns
21
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