HY51V(S)65163HG/HGL
4M x 16Bit EDO DRAM
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.0.1/Apr.01
DESCRIPTION
This familiy is a 64Mbit dynamic RAM organized 4,194,304 x 16bit configuration with Extended Data Out
mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read opera-
tion. The advanced circuit and process allow this device to achieve high performance and low power dissi-
pation. Features are access time(45ns or 50ns) and refresh cycle(4K ref ) and power consumption (Normal
or low power with self refresh).
Advanced CMOS process as well as circuit techniques for wide operating margins allow this device to
achieve high speed access and high reliability
FEATURES
Extended data out operation
Read-modify-write capability
Multi-bit parallel test capability
LVTTL(3.3V) compatible inputs and outputs
/RAS only, CAS-before-/RAS, Hidden and self
refresh(L-version) capability
Fast access time and cycle time
ODERING INFORMATION
Part No
tRAC
tAA
tCAC
tRC
tHPC
HY51V(S)65163HG/HGL-45
45ns
23ns
12ns
74ns
17ns
HY51V(S)65163HG/HGL-5
50ns
25ns
13ns
84ns
20ns
HY51V(S)65163HG/HGL-6
60ns
30ns
15ns
104ns
25ns
45ns
50ns
60ns
Active
468mW
432mW
396mW
Standby
1.8mW(CMOS level Max)
0.72mW (L-version : Max)
Part Number
Access Time
Package
HY51V(S)65163HG/HG(L)J-45
HY51V(S)65163HG/HG(L)J-5
HY51V(S)65163HG/HG(L)J-6
45ns
50ns
60ns
400mil 50pin SOJ
HY51V(S)65163HG/HG(L)T-45
HY51V(S)65163HG/HG(L)T-5
HY51V(S)65163HG/HG(L)T-6
45ns
50ns
60ns
400mil 50pin TSOP-II
PRELIMINARY
JEDEC standard pinout
50pin plastic SOJ/TSOP-II(400mil)
Single power supply of 3.3V +/- 10%
Battery back up operation(L-version)
Power dissipation
Refresh cycle
Part No
Ref
Normal
L-part
HY51V65163HG*
4K Ref
64ms
HY51V65163HGL*
4K Ref
128ms
* : /RAS only, CBR and hidden refresh
(S) : Self refresh, (L) : Low power