
HT49R50
25
October 22, 1999
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Input/output ports
Input/output ports
There are a 12-bit bidirectional input/output
port, an 8-bit input port in the HT49R50, la-
beled PA, PB and PC which are mapped to
[12H], [14H] and [16H] of the RAM, respec-
tively. PA0~PA3 can be configured as CMOS
(output) or NMOS (input/output) with or
without pull-high resistor by options. PA4~PA7
are always pull-high and NMOS (input/output).
If you choose NMOS (input), each bit on the port
(PA0~PA7)canbeconfiguredasawake-upinput.
PBcanonlybeusedforinputoperation,andeach
bit on the port can be configured with pull-high
resistor.PCcanbeconfiguredasCMOSoutputor
NMOSinput/outputwithorwithoutpull-highre-
sistor by options. All the port for the input opera-
tion (PA, PB and PC), these ports are
non-latched,thatis,theinputsshouldbereadyat
the T2 rising edge of the instruction MOV A,
[m] (m=12H or 14H). For PA, PC output opera-
tion, all data are latched and remain unchanged
until the output latch is rewritten.
When the PA and PC structures are open drain
NMOS type, it should be noted that, before
reading data from the pads, a 1
written to the related bits to disable the NMOS
device. That is executing first the instruction
"SET [m].i" (i=0~7 for PA) to disable related
NMOS device, and then "MOV A, [m]" to get
stable data.
should be
After chip reset, these input lines remain at the
high level or are left floating (by options). Each
bit of these output latches can be set or cleared
by the "SET [m].i" and "CLR [m].i" (m=12H or
16H) instructions.
Some instructions first input data and then fol-
low the output operations. For example, "SET
[m].i", "CLR [m].i", "CPL [m]", "CPLA[m]" read
the entire port states into the CPU, execute the
defined operations (bit-operation), and then
write the results back to the latches or to the ac-
cumulator.