
HT49R30A-1/HT49C30-1/HT49C30L
Rev. 1.10
19
September 25, 2002
ThePFDoutputsignalfunctioniscontrolledbythePA3dataregisterandthetimer/eventcounterstate.ThePFDoutput
signal frequency is also dependent on the timer/event counter overflow period. The definitions of PFD control signal
and PFD output frequency are listed in the following table.
Timer
Timer Preload Value
PA3 Data Register
PA3 Pad State
PFD Frequency
OFF
X
0
U
X
OFF
X
1
0
X
ON
N
0
PFD
f
INT
/[2 (256 N)]
ON
N
1
0
X
Note:
X stands for unused
U stands for unknown
F
1
F
' *
-
'
%
'
' )
-
>
;
7
# '
= 9
-
>
= = ;
# ( /
# 0
7
# ( /
#
9 '
7
# ( /
#
9 '
'
' )
-
>
= = ;
* ( /
* 3
)
PA Input/output ports
PB Input ports
LCD display memory
The device provides an area of embedded data memory
for LCD display. This area is located from 40H to 52H of
the RAM at Bank 1. Bank pointer (BP; located at 04H of
the RAM) is the switch between the RAM and the LCD
display memory. When the BP is set as 01H , any data
written into 40H~52H will effect the LCD display. When
the BP is cleared to
40H~52H means to access the general purpose data
00H , any data written into
memory. The LCD display memory can be read and
written to only by indirect addressing mode using MP1.
When data is written into the display data area, it is auto-
matically read by the LCD driver which then generates
the corresponding LCD driving signals. To turn the dis-
play on or off, a 1 or a 0 is written to the correspond-
ing bit of the display memory, respectively. The figure
illustrates the mapping between the display memory
and LCD pattern for the device.
( 4
(
4
4
4
3 (
*
(
(
5
0
2
3
3
Display memory