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參數(shù)資料
| 型號： | HT48RB8 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit USB Type OTP MCU |
| 中文描述： | 8位微控制器的USB型檢察官辦公室 |
| 文件頁數(shù)： | 17/45頁 |
| 文件大小： | 281K |
| 代理商： | HT48RB8 |
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HT48RB8
Rev. 1.30
17
February 10, 2003
Input/Output Ports
There are 32 bidirectional input/output lines in the
microcontroller, labeled from PA to PD, which are
mapped to the data memory of [12H], [14H], [16H] and
[18H] respectively. All of these I/O ports can be used for
input and output operations. For input operation, these
ports are non-latching, that is, the inputs must be ready
at the T2 rising edge of instruction MOVA,[m] (m=12H,
14H, 16H or 18H). For output operation, all the data is
latched and remains unchanged until the output latch is
rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS/NMOS/PMOS output
or Schmitt trigger input with or without pull-high/low re-
sistor structures can be reconfigured dynamically (i.e.
on-the-fly) under software control. To function as an in-
put, the corresponding latch of the control register must
write 1 . The input source also depends on the control
register. If the control register bit is 1 , the input will
read the pad state. If the control register bit is 0 , the
contents of the latches will move to the internal bus. The
latter is possible in the read-modify-write instruction.
For output function, CMOS/NMOS/PMOS configura-
tions can be selected (NMOS and PMOS are available
forPAonly).Thesecontrolregistersaremappedtoloca-
tions 13H, 15H, 17H and 19H.
Afterachipreset,theseinput/outputlinesremainathigh
levels or floating state (depending on the pull-high/low
options). Each bit of these input/output latches can be
set or cleared by SET [m].i and CLR [m].i (m=12H,
14H, 16H or 18H) instructions.
Some instructions first input data and then follow the
output operations. For example,
SET [m].i ,
CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device.
There are pull-high/low (PA only) options available for
I/O lines. Once the pull-high/low option of an I/O line is
selected, the I/O line have pull-high/low resistor. Other-
wise, the pull-high/low resistor is absent. It should be
noted that a non-pull-high/low I/O line operating in input
mode will cause a floating state.
It is recommended that unused or not bonded out I/O
linesshouldbesetasoutputpinsbysoftwareinstruction
to avoid consuming power under input floating state.
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Input/output ports
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