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參數(shù)資料
| 型號： | HT48E06 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit I/O Type MCU (With EEPROM) |
| 中文描述： | 8位I / O型微控制器（帶EEPROM） |
| 文件頁數(shù)： | 15/43頁 |
| 文件大?。?/td> | 346K |
| 代理商： | HT48E06 |
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HT48E06
Rev. 0.00
15
January 12, 2004
Preliminary
Input/Output Ports
There are 13 bidirectional input/output lines in the
microcontroller, labeled from PA to PC, which are
mapped to the data memory of [12H], [14H], [16H] re-
spectively. All of these I/O ports can be used for input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction MOV A,[m] (m=12H, 14H
or 16H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC) to control the input/output configuration. With this
control register, CMOS output or Schmitt trigger input
with or without pull-high resistor structures can be re-
configured dynamically under software control. To func-
tion as an input, the corresponding latch of the control
register must write a 1 . The input source also depends
on the control register. If the control register bit is 1 ,
the input will read the pad state. If the control register bit
is 0 , the contents of the latches will move to the inter-
nal bus. The latter is possible in the read-modify-write
instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H and 17H.
Afterachipreset,theseinput/outputlinesremainathigh
levels or in a floating state (depending on the pull-high
options). Each bit of these input/output latches can be
set or cleared by SET [m].i and CLR [m].i (m=12H,
14H or 16H) instructions.
Some instructions first input data and then follow the
output operations. For example,
SET [m].i ,
CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port Ahas the capability of waking-up the de-
vice. The highest 6-bit of port C and 5-bit of port B are not
physically implemented; on reading them a 0 is returned
whereas writing then results in no operation. See Applica-
tion note.
There is a pull-high option available for all I/O lines (bit
option). Once the pull-high option of an I/O line is se-
lected, the I/O line has a pull-high resistor. Otherwise,
the pull-high resistor is absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
The PB0 and PB1 are pin-shared with BZ and BZ, re-
spectively. If the BZ/BZ option is selected, the output
signal in output mode of PB0/PB1 will be the PFD signal
generated by the Timer/Event Counter 0 overflow sig-
nal. The input mode always remain in its original func-
tions. Once the BZ/BZ option is selected, the buzzer
output signals are controlled by the PB0 data register
only.
The I/O functions of PB0/PB1 are shown below.
PB0 I/O
I
I
I
I
O
O
O
O
O
O
PB1 I/O
I
O
O
O
I
I
I
O
O
O
PB0/PB1 Mode
x
C
B
B
C
B
B
C
B
B
PB0 Data
x
x
O
I
D
O
I
D
0
O
I
PB1 Data
x
D
x
x
x
x
x
D
1
x
x
PB0 Pad Status
I
I
I
I
D
O
B
D
0
O
B
PB1 Pad Status
I
D
O
B
I
I
I
D
1
O
B
Note:
I input,
B buzzer option, BZ or BZ,
C CMOS output
O output,
D, D
0
, D
1
data,
x don t care
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