參數(shù)資料
型號(hào)： HT48E06
廠商： Holtek Semiconductor Inc.
英文描述： 8-Bit I/O Type MCU (With EEPROM)
中文描述： 8位I / O型微控制器（帶EEPROM）
文件頁數(shù)： 13/43頁
文件大?。?/td> 346K
代理商： HT48E06
HT48E06
Rev. 0.00
13
January 12, 2004
Preliminary
The registers status is summarized in the following table.
Register
Reset
(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
TMR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
Program
Counter
000H
000H
000H
000H
000H
MP
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
--00 -000
--00 -000
--00 -000
--00 -000
--uu -uuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
---- -111
---- -111
---- -111
---- -111
---- -uuu
PBC
---- -111
---- -111
---- -111
---- -111
---- -uuu
PC
---- --11
---- --11
---- --11
---- --11
---- --uu
PCC
---- --11
---- --11
---- --11
---- --11
---- --uu
EECR
1000 ----
1000 ----
1000 ----
1000 ----
uuuu ----
Note:
* stands for warm reset
u stands for unchanged
x stands for unknown
Timer/Event Counter
A timer/event counter (TMR) is implemented in the
microcontroller. The timer/event counter contains an
8-bit programmable count-up counter and the clock may
comefromanexternalsourceorfromthesystemclock.
Using an external clock input allows the user to count
external events, measure time internals or pulse widths,
or generate an accurate time base. Using the internal
clockallowstheusertogenerateanaccuratetimebase.
The timer/event counter can generate PFD signals by
using external or internal clock and the PFD frequency
is determine by the equation f
INT
/[2 (256-N)].
There are two registers related to the timer/event coun-
ter; TMR ([0DH]), TMRC ([0EH]). Two physical registers
are mapped to TMR location; writing to TMR makes the
starting value be placed in the timer/event counter
preload register and reading TMR retrieves the contents
of the timer/event counter. The TMRC is a timer/event
counter control register, which defines some options.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
whichmeansthattheclocksourcecomesfromanexter-
nal (TMR) pin. The timer mode functions as a normal
timer with the clock source coming from the f
INT
clock.
The pulse width measurement mode can be used to count
the high or low level duration of the external signal (TMR).
The counting is based on the f
INT
clock.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFH. Once over-
flow occurs, the counter is reloaded from the timer/event
counter preload register and generates the interrupt re-
quest flag (TF; bit 5 of the INTC) at the same time.
In the pulse width measurement mode with the TON and
TE bits equal to one, once the TMR has received a tran-
sient from low to high (or high to low if the TE bit is 0 ) it
will start counting until the TMR returns to the original
level and resets the TON. The measured result will re-
main in the timer/event counter even if the activated
transient occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it re-
ceives further transient pulse. Note that, in this operat-
ing mode, the timer/event counter starts counting not
according to the logic level but according to the transient
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