
ing the programmer to use the structure easily.
Likewise, if the stack is full and a CALL is
subsequently executed, a stack overflow will
occur and the first entry will be lost (only the
most recent four return addresses will be
stored).
Data memory – RAM
The data memory (RAM) is composed of bits
ranging from 81
×
8, 113
×
8, 184
×
8, or 255
×
8, de-
pending on the microcontroller chosen
(HT48C10/ HT48C30/HT48C50/HT48C70). It is
divided into two functional groups, i.e., special
function registers and general purpose data
memory (of 64
×
8, 96
×
8, 160
×
8, or 224
×
8 bits,
depending on the microcontroller selected
(HT 48C10/ HT 48C30/HT 48C50/HT 48C70).
Most components of the two functional groups
are readable/writable, but some are read-only.
Of the two functional groups, the special func-
tion registers of the four microcontrollers con-
sist of a program counter lower-order byte
register (PCL ;06H), an accumulator (ACC;
05H), a table pointer (TBL P;07H), a table
higher-order byte register (TBL H;08H), a
status register (STATUS;0AH), an interrupt
control register (INTC;0BH), a watchdog timer
option setting register (WDTS;09H), an indirect
addressing register (00H), a memory pointer
register (MP;01H), a timer/event counter
(TMR;0DH), a timer/event counter control reg-
ister
(T MR C ;0E H ),
(PA;12H,PB;14H, PC;16H), and I/O control reg-
isters (PAC;13H,PBC;15H,PCC;17H). But of
the HT48C50/HT48C70, the following compo-
nents are further divided into two or several
sub-components. First, the indirect addressing
register is divided into two registers involving
indirect addressing register 0 (00H) and indi-
rect addressing register 1 (02H). Second, the
memory pointer register is also comprised by
two registers involving memory pointer register
0 (MP0;01H) and memory pointer register 1
(MP1;03H). Third, the timer/event counter reg-
ister is organized by two registers according to
different orders of byte, namely timer/event
higher-order byte register and timer/event
lower-order byte register, both of which are fur-
ther divided into timer/event counter 0 higher-
I/O
registers
order byte register (TMR0H; 0CH), timer/ event
counter 1 higher-order byte register
(TMR1H;0FH), timer/event counter 0 lower-or-
der byte register (T MR 0L ;0DH ), and
timer/event counter 1 lower-order byte register
(TMR1L;10H). Fourth, the timer/event counter
control register is divided into two registers
involving timer/event counter 0 control register
RAM mapping
HT48CXX/HT48RXX
16
25th May ’99