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參數(shù)資料
| 型號： | HT48CXX |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit Microcontroller Series |
| 中文描述： | 8位微控制器系列 |
| 文件頁數(shù)： | 13/59頁 |
| 文件大小： | 2625K |
| 代理商： | HT48CXX |
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Functional Description
The four microcontrollers of the HT48C10/
HT48C30/HT48C50/HT48C70 are constructed
using basically the same principles. Their dif-
ferences lie in variations in sizes such as ROM
and RAM as well as bit number, counter num-
ber, I/O line number, and different level subrou-
tine nesting bit number. The following is a more
detailed description of the system architectures
of the four microcontrollers. Unless specified,
the architecture stated below exists in these
four microcontrollers.
Execution flow
The system clock is derived from either a crystal
or an RC oscillator. It is internally divided into
four non-overlapping clocks. E ach instruction
cycle consists of four system clock cycles.
Instruction fetching and execution are pipe-
lined in such a way that a fetch takes one in-
struction cycle while decoding and execution
takes the next instruction cycle. The pipelining
scheme causes each instruction to effectively
execute in a cycle. If an instruction changes the
program counter, two cycles are required to
complete the instruction.
Program counter – PC
The program counter (PC) is of different sizes
ranging from 10 bits to 13 bits according to the
microcontroller selected (10 bits for the
HT48C10; 11 bits for the HT48C30; 12 bits for
the HT48C50; 13 bits for the HT48C70). It con-
trols a sequence in which the instructions
stored in the program ROM are executed. The
contents of the PC can specify 1024, 2048, 4096,
or 8192 addresses at maximum, according to
the microcontroller (H T 48C10/H T 48C30/
HT48C50/HT48C70) chosen.
After accessing a program memory word in or-
der to fetch an instruction code, the contents of
the PC is incremented by one. The PC then
points to the memory word consisting of the
next instruction code.
When executing a jump instruction, conditional
skip execution, loading a PCL register, a sub-
routine call, an initial reset, an internal inter-
rupt, an external interrupt, or returning from a
subroutine, the PC manipulates a program
transfer by loading the address corresponding
to each instruction.
The conditional skip is activated by instructions.
Once the condition is met, the next instruction,
fetched during the current instruction execution,
is discarded and a dummy cycle replaces it to get
a proper instruction; otherwise it proceeds to the
next instruction.
The lower byte of the PC (PCL) is a readable
and writeable register (06H). Moving data into
the PCL performs a short jump. The destination
is within 256 locations.
For a control transfer to take place, an addi-
tional dummy cycle is required.
E xecution flow
HT48CXX/HT48RXX
13
25th May ’99
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HT48E06 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:8-Bit I/O Type MCU (With EEPROM) |
| HT48E10 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:I/O Type 8-Bit MTP MCU With EEPROM |
| HT48E10_0610 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:I/O Type 8-Bit MTP MCU With EEPROM |
| HT48E30 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:I/O Type 8-Bit MTP MCU With EEPROM |
| HT48E50 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:I/O Type 8-Bit MTP MCU With EEPROM |
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