參數(shù)資料
型號: HT24LC04-8DIP-A
元件分類: EEPROM
英文描述: EEPROM
中文描述: EEPROM的
文件頁數(shù): 4/12頁
文件大?。?/td> 100K
代理商: HT24LC04-8DIP-A
HT24LC02
Rev. 1.10
4
November 5, 2002
Functional Description
Serial clock (SCL)
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
Serial data (SDA)
The SDA pin is bidirectional for serial data transfer.
The pin is open-drain driven and may be wired-OR
with any number of other open-drain or open collector
devices.
A0, A1, A2
TheA2,A1andA0pinsaredeviceaddressinputsthat
are hard wired for the HT24LC02. As many as eight
2K devices may be addressed on a single bus system
(the device addressing is discussed in detail under the
Device Addressing section).
Write protect (WP)
The HT24LC02 has a write protect pin that provides
hardware data protection. The write protect pin allows
normal read/write operations when connected to the
V
SS
. When the write protect pin is connected to Vcc,
the write protection feature is enabled and operates
as shown in the following table.
WP Pin
Status
Protect Array
At V
CC
Full Array (2K)
At V
SS
Normal Read/Write Operations
Memory organization
HT24LC02, 2K Serial EEPROM
Internally organized with 256 8-bit words, the 2K re-
quiresan8-bitdatawordaddressforrandomwordad-
dressing.
Device operations
Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
Start condition
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
Stop condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (re-
fer to Start and Stop Definition Timing Diagram).
Acknowledge
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has re-
ceivedeachword.Thishappensduringtheninthclock
cycle.
Device addressing
The 2K EEPROM devices all require an 8-bit device ad-
dress word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to the diagram showing
the Device Address). This is common to all the
EEPROM device.
The next three bits are the A2, A1 and A0 device ad-
dress bits for the 2K EEPROM. These three bits must
compare to their corresponding hard-wired input pins.
The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
Write operations
Byte write
A write operation requires an 8-bit data word address
following the device address word and acknowledg-
ment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing de-
vice, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
non-volatile memory. All inputs are disabled during
this write cycle and EEPROM will not respond until the
write is completed (refer to Byte write timing).
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