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參數(shù)資料
| 型號(hào)： | HSP48908GC-32 |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | Two Dimensional Convolver |
| 中文描述： | 8-BIT, DSP-CONVOLVER, CPGA84 |
| 封裝： | PGA-84 |
| 文件頁(yè)數(shù)： | 13/18頁(yè) |
| 文件大?。?/td> | 110K |
| 代理商： | HSP48908GC-32 |
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the cascade inputs CASI0-15 to go to the multiplier array.
The inputs of one external row buffer (such as the HSP9500)
are connected to the input data in parallel with the DlN0-7
lines of the convolver; and its outputs are connected to the
CASl0-7 inputs (See Figure 4). A second external row buffer
is connected between the outputs of the first row buffer and
the CASl8-15 inputs of the convolver. The convolution
operation can then be performed by the HSP48908 in the
same manner as the single chip mode. The row length in this
configuration is limited only by the maximum length of the
external row buffers. Note that when using the convolver in
this configuration, the programmable input data delays and
ALU will only operate on the data entering the DIN0-7 inputs
(i.e., the bottom row of the 3 x 3 sum of products). If higher
order filters or pixel point operations are required when using
external row buffers, these functions must be implemented
externally by the user.
Cascading Multiple HSP48908s
Multiple HSP48908s are capable of being cascaded to per-
form convolution on images with row lengths longer than
1024 pixels and with kernel sizes larger than 3 x 3. Figure 5
illustrates the use of two HSP48908s to perform a 3 x 3 ker-
nel convolution on a 2K x N frame. In this case, the cascade
mode control bit (Bit 0) of both Initialization Registers are set
to a ‘0’. The loading of the coefficients is accomplished just
as before. However, the 3 x 3 mask is divided into two por-
tions for proper convolution output as follows: Convolver #1 =
DEF000GHl and Convolver #2 = ABC000000.
The same configuration can be used to perform 3 x 5
convolution on a 1K x N frame simply by setting up the
coefficients of the convolvers to implement the 3 x 5 mask as
indicated below:
In addition to larger frames, larger kernels can also be
addressed through cascadability. An example of the
configuration for a 5 x 5 kernel convolution on a 1K x N
frame is shown in Figure 6. Note that in this configuration,
convolver #2 incorporates a 3 clock cycle delay (z -3) and
convolvers 3 and 4 incorporate 2 clock cycle delays (z -2) at
their pixel inputs. These delays are required to ensure
proper data alignment in the final sum of products output of
the cascaded convolvers. The number of delays required at
the pixel input is programmable through the use of bits 1 and
2 of the Initialization Register (Refer to Table 3).
IMAGE
DATA
FILTERED
IMAGE
DATA
ROW
BUFFER
ROW
BUFFER
20
8
DIN0 - 7
DOUT0 - 19
HSP48908
CASI0 - 7
CASI0 - 16
FIGURE 4. USING EXTERNAL ROW BUFFERS WITH THE
HSP48908
3 x 3 FILTER
KERNEL
COEFFICIENT MASKS
CONVOLVER #1
CONVOLVER #2
A B C
D E F
A B C
D E F
0 0 0
0 0 0
G H I
G H I
0 0 0
3 x 5 FILTER
KERNEL
CONVOLVER COEFFICIENT MASKS
A B C
G H I
A B C
D E F
J K L
D E F
G H I
M N O
0 0 0
J K L
M N O
IMAGE
DATA
FILTERED
IMAGE
DATA
20
8
DIN0 - 7
DOUT0 - 19
HSP48908
#1
CASI0 - 15
FIGURE 5. 3 x 3 KERNAL CONVOLUTION ON A 2K x N IMAGE
CASO0 - 7
DIN0 - 7
DOUT0 - 19
HSP48908
#2
CASI0 - 15
CASO0 - 7
Z
-2
HSP48908
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50016GC-52 | Digital Down Converter |
| HSP50016-EV | DDC Evaluation Platform |
| HSP50016JC-52 | Digital Down Converter |
| HSP50016JC-75 | Digital Down Converter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP48908GM-20/883 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Two Dimensional Convolver |
| HSP48908GM-27/883 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Two Dimensional Convolver |
| HSP48908JC-20 | 制造商:Rochester Electronics LLC 功能描述:3 X 3 2D CONVOLVER 84 PLCC, 20MHZ, COMM - Bulk |
| HSP48908JC-32 | 制造商:Rochester Electronics LLC 功能描述:3 X 3 2D CONVOLVER 84 PLCC, 32MHZ, COMM - Bulk |
| HSP48908VC-20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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