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參數(shù)資料
| 型號： | HSP45256JI-25 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字信號處理外設 |
| 英文描述： | Binary Correlator |
| 中文描述： | 8-BIT, DSP-CORRELATOR, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 154K |
| 代理商： | HSP45256JI-25 |
10
TABLE 2. MASK REGISTER
DESTINATION ADDRESS = 0 (000)
BIT
POSITIONS
FUNCTION
DESCRIPTION
7-0
Mask Register
Bit Enable
MR(7:0): Mask Register. When mask register bit N = 1, the corresponding reference register bit is en-
abled. Mask register data is loaded from the DCONT(7:0) bus into a holding register on the rising edge
of CLOAD and is written to the mask register on the rising edge of TXFR.
TABLE 3. CONFIGURATION REGISTER
DESTINATION ADDRESS = 1 (001)
BIT
POSITION
FUNCTION
DESCRIPTION
7-6
Reserved
Reserved; Program to zero.
5
TC
Configures correlator for twos complement input format, where the position of the MSB is depends on
the current configuration. TC = 1 is twos complement; TC = 0 is offset binary.
4
CONFIG(4)
CONFIG4: The state of CONFIG4 configures the HSP45256 as either one or two correlators. When
CONFIG4 = 0, the HSP45256 is configured as one correlator with the correlation score available on
CASOUT0-12.
When CONFIG4 = 1, the HSP45256 is configured as dual correlators with the first correlators score
available on CASOUT0-8 and the second score available on AUXOUT0-8. When the chip is configured
as dual correlators, the Programmable Delay must be set to 0000 for a delay of 1.
3-2
CONFIG(3:2):
CONFIG(3:2): Control the number of data bits to be correlated. See Table 9.
1-0
CONFIG(1:0)
CONFIG(1:0): CONFIG1 and CONFIG0 represent the length of the correlation window as indicated in
Table 9.
TABLE 4. MS OFFSET REGISTER A
DESTINATION ADDRESS = 2 (010)
BIT
POSITION
FUNCTION
DESCRIPTION
7-5
Reserved
Reserved. Program to zero.
4-0
Offset Register A MSB
OFFA(12:8): Most significant bits of Offset Register A. This is the register used in single correlator
mode.
TABLE 5. LS OFFSET REGISTER A
DESTINATION ADDRESS = 3 (011)
BIT
POSITION
FUNCTION
DESCRIPTION
7-0
Offset Register A LSB
OFFA(7:0): Least significant bits of Offset Register A.
TABLE 6. PROGRAMMABLE DELAY REGISTER
DESTINATION ADDRESS = 4 (100)
BIT
POSITION
FUNCTION
DESCRIPTION
7-4
Reserved
Reserved. Program to zero.
3-0
Programmable Delay
PDELAY(3:0): Controls amount of delay from the weight and sum logic to the cascade summer. The
number of delays is 1-16, with PDELAY = 0000 corresponding to a delay of 1 and PDELAY = 1111 cor-
responding to a delay of 16.
HSP45256
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PDF描述 |
|---|---|
| HSP45256JI-33 | Binary Correlator |
| HSP45256 | Binary Correlator |
| HSP45256883 | Binary Correlator |
| HSP45256JC-25 | Binary Correlator |
| HSP45256JC-33 | Binary Correlator |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HSP45256JI-33 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Binary Correlator |
| HSP45314 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CommLinkTM Direct Digital Synthesizer |
| HSP45314_01 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CommLinkTM Direct Digital Synthesizer |
| HSP45314VI | 制造商:Rochester Electronics LLC 功能描述:DIRECT DIGITAL SYNTHESIZER - Bulk |
| HS-P4-775 | 制造商:Itox, Inc. 功能描述:P4 SOCKET 775 HEAT SINK - Bulk |
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