參數(shù)資料
型號(hào)： HSP45256JC-33
廠商： HARRIS SEMICONDUCTOR
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： Binary Correlator
中文描述： 8-BIT, DSP-CORRELATOR, PQCC84
文件頁(yè)數(shù)： 8/23頁(yè)
文件大小： 154K
代理商： HSP45256JC-33
8
The function performed by one correlation cell is:
(D
i,n
XNOR R
i,n
) AND M
i,n
where:
D
i,n
= Bit i of data register n
R
i,n
= Bit i of reference register n
M
i,n
= Bit i of mask register n
The reference and mask bits are loaded sequentially, N bits
at a time, where N depends on the current configuration (see
Tables 2 and 9). New reference data is loaded on the rising
edge of RLOAD and new mask data is loaded on the rising
edge of CLOAD. The mask and reference bits are stored
internally in Shift Registers, so that the mask and reference
information that was loaded most recently will be used to
process the newest data. When new information is loaded in,
the previous contents of the mask and reference bits are
shifted over by one sample, and the oldest information is
lost. There are no registers in the multiplexer array (see
Block Diagram), so the data on DOUT0-7 corresponds to the
data in the last element of the correlation array. When
monitoring DOUT0-7, AUXOUT0-8, and REFOUT0-7, only
those bits listed in Table 9 are valid.
FIGURE 3. CORRELATION CELL BLOCK DIAGRAM
FIGURE 4. CORRELATION CELL TIMING DIAGRAM
R
E
G
>
RLOAD
DREF
R
E
G
>
DCONT
(MASK)
CLOAD
DREFOUT
DCONTOUT
R
E
G
>
TXFR
R
E
G
>
CLK
DATA
DATAOUT
COROUT
A
B
R
E
G
>
RLOAD
DREF
DCONT
CLOAD
TXFR
CLK
DATA
DATA CONTROL
A
B
DR8
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
DR-1
D7
D6
D5
D4
D3
D2
D1
D0
D-1
HSP45256
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