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參數(shù)資料
| 型號： | HSP45256JC-33 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Binary Correlator |
| 中文描述： | 8-BIT, DSP-CORRELATOR, PQCC84 |
| 文件頁數(shù)： | 22/23頁 |
| 文件大?。?/td> | 154K |
| 代理商： | HSP45256JC-33 |
22
Test Load Circuit
Set-Up Time DIN to CLK High
t
DS
12
-
13
-
ns
Hold Time CLK High to DIN
t
DH
0
-
0
-
ns
TXFR Set-Up Time
t
TS
12
-
13
-
ns
TXFR Hold Time
t
TH
0
-
0
-
ns
Output Delay DOUT, AUXOUT, CASOUT
t
DO
-
15
-
20
ns
CLOAD Cycle Time
t
CLC
30
-
39
-
ns
CLOAD High
t
CLH
12
-
15
-
ns
CLOAD Low
t
CLL
12
-
15
-
ns
Set-Up Time, A to RLOAD, CLOAD
t
AS
12
-
13
-
ns
Hold Time, RLOAD, CLOAD to A
t
AH
0
-
0
-
ns
RLOAD Cycle Time
t
RLC
30
-
39
-
ns
RLOAD High
t
RLH
12
-
15
-
ns
RLOAD Low
t
RLL
12
-
15
-
ns
Set-Up Time, DCONT to CLOAD
t
DCS
12
-
13
-
ns
Hold Time, CLOAD to DCONT
t
DCH
0
-
0
-
ns
Set-Up Time, DREF to RLOAD
t
RS
12
-
13
-
ns
Hold Time, RLOAD to DREF
t
RH
0
-
0
-
ns
Output Enable Time
t
OE
-
15
-
15
ns
Output Disable Time
t
OD
Note 6
-
15
-
15
ns
Output Rise, Fall Time
t
RF
Note 6
-
6
6
ns
TXFR High to CLK Low
t
THCL
Note 6
3
-
3
-
ns
CLK Low to RLOAD, CLOAD High
t
CLLH
Note 6
1
-
1
-
ns
NOTES:
5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; Input levels (all other inputs) 0V and 3.0V; Timing reference levels
(CLK) 2.0V; All others 1.5V. Output load per test load circuit with C
L
= 40pF. Output transition is measured at V
OH
> 1.5V and
V
OL
< 1.5V.
6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design
changes.
AC Electrical Specifications
V
CC
= 5.0V
±
5%, T
A
= 0
o
C to 70
o
C, T
A
= -40
o
C to 85
o
C, Note 5
(Continued)
PARAMETER
SYMBOL
NOTES
33MHz
25.6MHz
UNITS
MIN
MAX
MIN
MAX
DUT
EQUIVALENT CIRCUIT
1.5V
I
OL
I
OH
C
L
INCLUDES STRAY
AND JIG
CAPACITANCE
±
S
1
SWITCH S
1
OPEN FOR I
CCSB
AND I
CCOP
TEST
HSP45256
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