參數(shù)資料
型號(hào)： HSP45256JC-25
廠商： HARRIS SEMICONDUCTOR
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： Binary Correlator
中文描述： 8-BIT, DSP-CORRELATOR, PQCC84
文件頁(yè)數(shù)： 13/23頁(yè)
文件大?。?/td> 154K
代理商： HSP45256JC-25
13
During reference register loading, the 8-bits, DREF0-7 are
used as reference data inputs. The falling edge of RLOAD
initiates reference data loading; when RLOAD returns high,
the data on DREF0-7 is latched into the selected correlation
stages. The active bits on DREF0-7 are determined by the
current configuration.
The window configuration is determined by the state of control
signals upon programming the Control Register. Table 9
represents the programming information required for each
window configuration. In Table 9, note that the data listed for
Output Weighting refers to the weights given to each of the
Correlation Sum Outputs (CO0-7 in the Block Diagram).
During initialization, the loading configuration for the
reference data is set by the user. Table 9 shows the loading
options. These load controls specify whether the reference
data for a given stage comes from the shift register output of
the previous stage or from an external data pin.
Applications
There are 10 single correlator configurations possible with
the HSP45256. There are six dual correlator configurations
possible with the HSP45256. Table 10 details the
configuration (bits x rows x length) and the maximum
correlation sums of all combinations.
Single Correlator Configurations
1-Bit Data, Single Row, 256 Samples Configuration
A 1 x 256 (1-D configuration) correlation requires only 1
HSP45256. To initialize the correlator, all the reference bits,
control bits, the delay value of the variable delay, and the
window configuration must be specified. Table 11 details
these settings for the 1-bit data, 256 Samples Configuration.
Figure 5 illustrates the data flow through the correlator.
TABLE 10. CORRELATION SCORE FORMULAS FOR SINGLE CORRELATOR CONFIGURATIONS
FIGURE NUMBER
CONFIGURATION
BITS x ROWS x
LENGTH
HIGHEST POSSIBLE
TOTAL CORRELA-
TION SCORE
CORRELATION SCORE
Figure 5
1 x 1 x 256
256
CS=CO7+CO6+CO5+CO4+CO3+CO2+CO1+CO0
Figure 6
1 x 2 x 128
256
CS=CO7+CO6+CO5+CO4+CO3+CO2+CO1+CO0
Figure 7
1 x 4 x 64
256
CS=CO7+CO6+CO5+CO4+CO3+CO2+CO1+CO0
Figure 8
1 x 8 x 32
256
CS=CO7+CO6+CO5+CO4+CO3+CO2+CO1+CO0
Figure 9
2 x 1 x 128
384
CS=2(CO7+CO6+CO5+CO4)+CO3+ CO2+CO1+CO0
Figure 10
2 x 2 x 64
384
CS=2(CO7+CO6+CO5+CO4)+CO3+CO2+CO1+CO0
Figure 11
2 x 4 x 32
384
CS=2(CO7+CO6+CO5+CO4)+CO3+CO2+CO1+CO0
Figure 12
4 x 1 x 64
960
CS=8(CO7+CO6)+4(CO5+CO4)+2(CO3+CO2)+CO1+CO0
Figure 13
4 x 2 x 32
960
CS=8(CO7+CO6)+4(CO5+CO4)+2(CO3+CO2)+CO1+CO0
Figure 14
8 x 1 x 32
8160
CS=128C07+64CO6+32C05+16CO4+8CO3+4CO2+2CO1+CO0
Figure 15
1 x 1 x 128
1 x 1 x 128
128
CS=CO7+CO6+CO5+CO4CS=CO31CO2+CO1+CO0
Figure 16
1 x 2 x 64
1 x 2 x 64
128
CS=CO7+CO6+CO5+CO4CS=CO31CO2+CO1+CO0
Figure 17
1 x 4 x 32
1 x 4 x 32
128
CS=CO7+CO6+CO5+CORCS=CO31CO2+CO1+CO0
Figure 18
2 x 1 x 64
2 x 1 x 64
192
CS=2(CO7+CO6)+CO5+CO4CS=(CO3+CO2)+CO1+CO0
Figure 19
2 x 2 x 32
2 x 2 x 32
192
CS=2(CO7+CO6)+CO5+CO4CS=(CO3+CO2)+CO1+CO0
Figure 20
4 x 1 x 32
4 x 1 x 32
480
CS=8CO7+4CO6+2CO5+CO4CS= 8CO3+4CO2+2CO1+CO0
TABLE 11. REGISTER CONTENTS FOR 1 X 256 CORRELATOR
WITH EQUAL WEIGHTING
A0-2
DCONT0-7
NOTES
001
00000000
1 256-tap correlator: 1 x 256 window con-
figuration, reference loaded from DREF7,
eight stages weighted equally, DIN 7 and
DOUT7 are the data input and output, re-
spectively.
010
000000f00
Offset Register A = 0.
011
00000000
100
00000000
Programmable Delay = 0.
101
00000000
Offset Register B = 0 (Loading of this reg-
ister optional in this mode).
110
00000000
HSP45256
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