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參數資料
| 型號： | HSP45256JC-25 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 數字信號處理外設 |
| 英文描述： | Binary Correlator |
| 中文描述： | 8-BIT, DSP-CORRELATOR, PQCC84 |
| 文件頁數： | 7/23頁 |
| 文件大?。?/td> | 154K |
| 代理商： | HSP45256JC-25 |
7
Functional Description
The correlation array consists of eight 32-bit stages. The first
stage receives data directly from input pin DIN7. The other
seven stages receive input data from either an external data
pin, DIN0-6, or from the Shift Register output of the previous
stage, as determined by the Configuration Register. When
the part is configured as a single correlator the sum of
correlation score, Offset Register and cascade input
appears on CASOUT0-12. Delayed versions of the data and
reference inputs appear on DOUT0-7 and AUXOUT0-7,
respectively. The input and output multiplexers of the
correlation array are controlled together; for example, in a 1
x 256 correlation, the input data is loaded into DIN7 and the
output appears on DOUT7. The configuration of the data
bits, the length of the correlation (and in the two-dimensional
data, the number of rows), is commonly called the
correlation window. A top level Block Diagram of the single
correlator configuration is shown in Figure 1. Compare the
single correlator configuration data output and correlation
output to the top level Block Diagram of the dual correlator
configuration shown in Figure 2.
Correlator Array
The core of the HSP45256 is the correlation array, which
consists of eight 32-tap stages. A single correlator cell
consists of an XNOR gate for the individual bit comparison;
i.e., if the data and reference bits are either both high or both
low, the output of the correlator cell is high. Figure 3 details
the circuitry of a single correlation cell and Figure 4 shows
the timing for that single correlation cell. In addition, two
latches, one for the reference and one for the control data
path are contained in this cell. These latches are loaded
from the Preload Registers on the rising edge of CLK when
TXFR is low so that the reference and mask values are
updated without interrupting data processing.
The mask function is implemented with an AND gate. When
a mask bit is a logic low, the corresponding correlator cell
output is low.
8 32-BIT
CORRELATORS
DIN(7:0)
DREF(7:0)
DOUT(7:0)
SUM
WEIGHT
AND
SUM
CORR
SCORE
DELAY
SUM
OFFA
CASIN(12:0)
CASOUT(12:0)
AUXOUT(7:0)
FIGURE 1. SINGLE CORRELATOR CONFIGURATION
FIGURE 2. DUAL CORRELATOR CONFIGURATION
4 32-BIT
CORRELATORS
DIN(7:4)
DREF(7:4)
DOUT(7:4)
SUM
WEIGHT
AND
SUM
CORR
SCORE
DELAY
SUM
OFFA
CASOUT(8:0)
= 0000
CASIN(12:0)
4 32-BIT
CORRELATOR
DIN(3:0)
DOUT (3:0)
DREF(3:0)
SUM
CORR
SCORE
WEIGHT
AND
SUM
OFFB
AUXOUT(8:0)
CORRELATOR #1
CORRELATOR #2
HSP45256
相關PDF資料 |
PDF描述 |
|---|---|
| HSP45256JC-33 | Binary Correlator |
| HSP48410GC-33 | Histogrammer/Accumulating Buffer |
| HSP48410GC-40 | Histogrammer/Accumulating Buffer |
| HSP48410 | Histogrammer/Accumulating Buffer |
| HSP48410883 | Histogrammer/Accumulating Buffer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HSP45256JC-33 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Binary Correlator |
| HSP45256JI-25 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Binary Correlator |
| HSP45256JI-33 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Binary Correlator |
| HSP45314 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CommLinkTM Direct Digital Synthesizer |
| HSP45314_01 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CommLinkTM Direct Digital Synthesizer |
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