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參數(shù)資料
| 型號： | HSP45256883 |
| 廠商： | Intersil Corporation |
| 英文描述： | Binary Correlator |
| 中文描述： | 二元相關(guān)器 |
| 文件頁數(shù)： | 19/23頁 |
| 文件大?。?/td> | 154K |
| 代理商： | HSP45256883 |
19
Cascading Multiple Correlator Devices
Correlators can be cascaded in either a serial or parallel
fashion. Longer correlations can be achieved by connecting
several correlators together as shown in Figures 21- 23. In
Figure 21, each correlator is in a one data bit, one row, 256
tap configuration. The number of bits of significance at the
CASOUT output of each correlator builds up from one
correlation to the next, that is, the maximum score out of the
first correlator is 256, the maximum output of the second
correlator is 512, etc. In this configuration, the maximum
length of the correlation is 4096. This would be implemented
with 16 HSP45256’s. The Programmable Delay Register in
the first correlator would be set for one delay, the second
would be set for two, and so on, with the final HSP45256
being set for a delay of 16.
Correlations of more bits can be calculated by connecting
CASOUT of each chip to the CASIN of the following chip
(Figure 21). The data on the CASOUT lines accumulates in
a similar manner as in the 1 x 256 mode, except that the
maximum output of the first correlator is decimal 960,
(hexadecimal 3C0); in the general case, the maximum
number of correlators that can be cascaded in this manner is
eight, since the maximum output of the last one would be
1E00, which nearly uses up the 13-bit range of the cascade
summer. More parts could be cascaded together if some bits
are to be masked out or if the user has a prior knowledge of
the maximum value of the correlation score. As before, the
delay in the first correlator would be set to one, the second
correlator would be set for a delay of two, and so on.
Multiple HSP45256’s can be cascaded for two dimensional
one bit data (Figure 22). The maximum output for each chip
is the same as in the 1 x 256 case; the only difference is in
the manner in which the correlators are connected. The
programmable delay registers would be set as before.
FIGURE 21. 1-BIT, 1024 SAMPLE CONFIGURATION
FIGURE 22. 4-BIT, 256 SAMPLE CONFIGURATION
FIGURE 23. 1-BIT, 32 x 32 WINDOW CONFIGURATION
CORRELATOR
SCORE
OUTPUT
DIN7
CASIN0-12
CASOUT0-12
DOUT7
DATA INPUT
DIN7
CASIN0-12
CASOUT0-12
DOUT7
DIN7
CASIN0-12
CASOUT0-12
DOUT7
DIN7
CASIN0-12
CASOUT0-12
DOUT7
CORRELATOR
SCORE
OUTPUT
DIN7, 5, 3, 1
CASIN0-12
CASOUT0-12
DOUT7, 5, 3, 1
DATA INPUT
DIN7, 5, 3, 1
CASIN0-12
CASOUT0-12
DOUT7, 5, 3, 1
DIN7, 5, 3, 1
CASIN0-12
CASOUT0-12
DOUT7, 5, 3, 1
DIN7, 5, 3, 1
CASIN0-12
CASOUT0-12
DOUT7, 5, 3, 1
CORRELATOR
SCORE
OUTPUT
DIN0-7
CASIN0-12
CASOUT0-12
DATA INPUT
ROWS 0 - 7
DIN0-7
CASIN0-12
CASOUT0-12
DIN0-7
CASIN0-12
CASOUT0-12
DIN0-7
CASIN0-12
CASOUT0-12
DATA INPUT
ROWS 8 - 15
DATA INPUT
ROWS 16 - 23
DATA INPUT
ROWS 24 - 31
HSP45256
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP45256JC-25 | Binary Correlator |
| HSP45256JC-33 | Binary Correlator |
| HSP48410GC-33 | Histogrammer/Accumulating Buffer |
| HSP48410GC-40 | Histogrammer/Accumulating Buffer |
| HSP48410 | Histogrammer/Accumulating Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP45256GC-25 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Binary Correlator |
| HSP45256GC-33 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HSP45256GM-20/883 | 制造商:Rochester Electronics LLC 功能描述:BINARY CORRELATOR 85 PGA, 20MHZ, MIL 883 - Bulk 制造商:Harris Corporation 功能描述: |
| HSP45256GM-25/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Binary Correlator |
| HSP45256JC-25 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Binary Correlator |
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