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參數(shù)資料
| 型號(hào)： | HSP43881883 |
| 廠商： | Intersil Corporation |
| 英文描述： | Digital Filter |
| 中文描述： | 數(shù)字濾波 |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 148K |
| 代理商： | HSP43881883 |
8
The 26 least significant bits (LSBs) from either a cell
accumulator or the output buffer are output on the SUM0-25
bus. The output mux determines whether the cell
accumulator selected by ADR0-2 or the output buffer is
output to the bus. This mux is controlled by the SHADD input
signal. Control is based on the state of the SHADD during
two successive clocks; in other words, the output mux
selection contains memory. If SHADD is low during a clock
cycle and was low during the previous clock, the output mux
selects the contents of the filter cell accumulator addressed
by ADR0-2. Otherwise the output mux selects the contents
of the output buffer.
If the ADR0-2 lines remain at the same address for more
than one clock, the output at SUM0-25 will not change to
reflect any subsequent accumulator updates in the
addressed cell. Only the result available during the first clock
when ADR0-2 selects the cell will be output. This does not
hinder normal FIR operation since the ADR0-2 lines are
changed sequentially. This feature facilitates the interface
with slow memories where the output is required to be fixed
for more than one clock.
The SUM0-25 output bus is controlled by the SENBH and
SENBL signals. A low on SENBL enables bits SUM0-15. A
low on SENBH enables bits SUM16-25. Thus, all 26 bits can
be output simultaneously if the external system has a 26-bit
or larger bus. If the external system bus is only 16 bits, the
bits can be enabled in two groups of 16 and 10 bits (sign
extended).
DF Arithmetic
Both data samples and coefficients can be represented as
either unsigned or two's complement numbers. The TCS and
TCCI inputs determine the type of arithmetic representation.
Internally all values are represented by a 9-bit two's
complement number. The value of the additional ninth bit
depends on the arithmetic representation selected. For two's
complement arithmetic, the sign is extended into the ninth
bit. For unsigned arithmetic, bit-9 is 0.
The multiplier output is 18 bits and the accumulator is 26
bits. The accumulator width determines the maximum
possible number of terms in the sum of products without
MUX
CELL RESULT
18 (LSBs)
0-17
RESET.D
OUTPUT
BUFFER
18
CLR
D
26
26
26
26
0
1
6
7
3
26
OUTPUT
MUX
THREE-STATE
BUFFER
ZERO
MUX
0
1
0
18 MSBs SHIFTED
8 BITS TO RIGHT
(BITS 0 - 17)
8-25
CLK
Q
CLR
D
Q
CLK
26
26
26
CLK
26
SUM0-25
SHADD
SENBL
SENBH
2
SHADD.D
SIGN EXT
18-25
0-18
18
RESET.D
RESET.D
0
1
8
ADR0.D-ADR2.D
26
+
FIGURE 2. DF OUTPUT STAGE
HSP43881
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP43891GC-20 | Digital Filter |
| HSP43891GC-25 | Digital Filter |
| HSP43891GC-30 | Digital Filter |
| HSP43891JC-20 | Digital Filter |
| HSP43891JC-25 | Digital Filter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP43881GC-20 | 制造商:Harris Corporation 功能描述: |
| HSP43881GC-25 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HSP43881GC-30 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Filter |
| HSP43881GM-25/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Filter |
| HSP43881JC-20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
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